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Embedded Controller Modules (Continued)

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GENERAL-PURPOSE I/O (GPIO) PORTS

The PC87591x includes four types of General-Purpose I/O (GPIO) ports: Px, Py, Pz and Pw.

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Px signals: Each signal is bidirectional and can be conﬁgured as input or output. An internal weak pull-up is provided

to hold the pin high when used as an input or in an open-drain scheme.

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Py signals: Each signal is input only. An internal weak pull-up is provided to hold the pin high.

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Pz signals: Each signal is output only. It may be conﬁgured to work as totem-pole or in an open-drain scheme.

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Pw signals: Each signal is bidirectional and can be conﬁgured for input or output. The Pw pins may be shared with

development system functions. These ports can be implemented off-chip in DEV environment using external logic.

The GPIO signals are organized in ports. Each port is either 8-bits or 16-bits wide. In ports where not all eight bits are used,

some of the register’s bits are reserved. Some GPIO signals share their pins with one or more alternate functions. A config-

uration bit selects which function is active (see Section 2.4 on page 54).

Note: Some GPIO signals are only available in a 176-pin package.

GPIO Port Functionality

The PC87591x provides 117 GPIO pins in the 176-pin package and 84 GPIO pins in the 128-pin package. They are subdi-

vided into the following groups:

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Ports IOPA(7-0), IOPB(7-0), IOPC(7-0), IOPD(7-0) and IOPF(7-0)

These ports are on-chip, General-Purpose Input/Output (GPIO) ports (type Px).

IOPC0 is reserved for power supply control use. Bit 0 of PCALT, PCDIR, PCWPU and PCDOUT are reset on VCC Power-

Up reset and WATCHDOG reset only.

PB5 and PB6 have an option for automatic TRI-STATE based on LPCPD. See “MSWC Control Status Register 3

(MSWCTL3)” on page 330 for the enable function.

PB6 is selected to its alternate function, by default (i.e., bit 6 is set to 1).

Ports IOPA4-0, IOPB2-0, IOPC0 and IOPD3 have the option to echo the value of the associated input. For the exact

echo matrix specifications, see Section 2.4.3 on page 59.

Bit 5 of PBALT register, bit 0 of PCALT register and bits 4-7 of PDALT register are read only (RO) and return a value of

zero.

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IOPE(7-0) and KBSIN(7-0)

These are General-Purpose Input (GPI) ports (type Py). IOPE(3-0) and IOPE5 do not implement the pull-up function,

and the respective bits in PEWPU are reserved. KBSIN has no alternate function; thus it has no PyALT register.

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KBSOUT(15-0)

This is a 16-bit General-Purpose Output (GPO) port (type Pz). Since KBSOUT has no alternate functions, its alter-

nate function register is not implemented. The reset value of KBSOUT register is FFFF16. KBSOUT has open-drain

output drivers.

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Ports IOPH(7-0), IOPI(7-0), IOPJ(7-0), IOPK(7-0),IOPL(4-0) and IOPM(7-0)

These ports are on-chip, General-Purpose Input/Output (GPIO) ports (type Pw).

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When the analog function is enable, the Read function, for GPIO signals that are multiplexed with analog functions,

is disabled; this affects signals KBSIN(7-0) and IOPE(3-0).

When the BIU function is enabled, the Read function, for GPIO signals that are multiplexed with BIU signals, is dis-

abled; this affects signals PH(7-0), PI(7-0), PJ(1-0), PK(7-0), PL(7-0) and PM(7-0).

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