PC87591L datasheet(203/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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ACB Status Register (ACBnST)

The ACBnST register maintains current ACB status. Some of its bits may be cleared by software, as described below. On

reset, and when the module is disabled, ACBnST is cleared (0016).

Location: Channel - 1 00 FF6216

Channel - 2 00 FFE216

Type: varies per bit

Bit

76543210

Name

SLVSTP

SDAST

BER

NEGACK

STASTR

NMATCH

MASTER

XMIT

Reset

00000000

Bit

Type

Description

0RO

XMIT (Transmit Mode).

0: ACB not in master/slave Transmit mode

1: ACB in master/slave Transmit mode

1RO

MASTER (Master Mode).

0: Arbitration loss (BER is set) or Stop Condition occurred

1: ACB in Master mode (successful request for bus mastership)

R/W1C NMATCH (New Match). The bit is set when the address byte following a Start Condition or a

repeated start causes an address match, ARP address match or a global call match. NMATCH is

cleared by writing 1 to it. Writing 0 to NMATCH is ignored. If INTEN in ACBnCTL1 register is set, an

interrupt is sent when this bit is set.

R/W1C STASTR (Stall After Start). The bit is set by the successful completion of sending an address (i.e.,

a Start Condition sent without a bus error or negative acknowledge), if STASTRE in ACBnCTL1

pulling down the SCL line) and suspends any further action on the bus (e.g., receiving the ﬁrst byte

in Master Receive mode). In addition, if INTEN in ACBnCTL1 register is set, it also causes the ACB

module to send an interrupt to the core. Writing 1 to STASTR clears it. It is also cleared when the

module is disabled and is always cleared when STASTRE is cleared. Writing 0 to STASTR has no

effect.

R/W1C NEGACK (Negative Acknowledge). The bit is set by hardware when a transmission is not

acknowledged on the ninth clock (in this case, SDAST is not set). Writing 1 to NEGACK clears it. It is

also cleared when the module is disabled. Writing 0 to NEGACK is ignored.

R/W1C BER (Bus Error). The bit is set by the hardware when a Start or Stop Condition is detected during

data transfer (i.e., Start or Stop Condition during the transfer of bits 2 through 8 and acknowledge

cycle) or when an arbitration problem is detected. Writing 1 to BER clears it. It is also cleared when

the module is disabled. Writing 0 to BER is ignored.

6RO

SDAST (SDA Status). When set, this bit indicates that the SDA data register is waiting for data

(Transmit mode - master or slave) or holds data that should be read (Receive mode - master or

slave). This bit is cleared when reading from ACBnSDA register during a receive or when written to

during a transmit. When START in the ACBnCTL1 is set, reading ACBnSDA register does not clear

SDAST. This enables the ACB to send a repeated start in Master Receive mode.

R/W1C SLVSTP (Slave Stop). When set, SLVSTP indicates that a Stop Condition was detected after a slave

transfer (i.e., after a slave transfer in which MATCH or GCMATCH was set). Writing 1 to SLVSTP

clears it. It is also cleared when the module is disabled. Writing 0 to SLVSTP is ignored.

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