24

CC2650MODA

SWRS187A – AUGUST 2016 – REVISED AUGUST 2016

www.ti.com

Submit Documentation Feedback

Product Folder Links: CC2650MODA

Detailed Description

Copyright © 2016, Texas Instruments Incorporated

6.3

Main CPU

The SimpleLink CC2650MODA wireless MCU contains an ARM Cortex-M3 (CM3) 32-bit CPU, which runs

the application and the higher layers of the protocol stack.

The CM3 processor provides a high-performance, low-cost platform that meets the system requirements

of

minimal

memory

implementation,

and

low-power

consumption,

while

delivering

outstanding

computational performance and exceptional system response to interrupts.

CM3 features include:

•

32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications

•

Outstanding processing performance combined with fast interrupt handling

•

ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the

range of a few kilobytes of memory for microcontroller-class applications:

–

Single-cycle multiply instruction and hardware divide

–

Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral

control

–

Unaligned data access, enabling data to be efficiently packed into memory

•

Fast code execution permits slower processor clock or increases sleep mode time

•

Harvard architecture characterized by separate buses for instruction and data

•

Efficient processor core, system, and memories

•

Hardware division and fast digital-signal-processing oriented multiply accumulate

•

Saturating arithmetic for signal processing

•

Deterministic, high-performance interrupt handling for time-critical applications

•

Enhanced system debug with extensive breakpoint and trace capabilities

•

Serial wire trace reduces the number of pins required for debugging and tracing

•

Migration from the ARM7™ processor family for better performance and power efficiency

•

Optimized for single-cycle flash memory use

•

Ultra-low-power consumption with integrated sleep modes

•

1.25 DMIPS per MHz

6.4

RF Core

The RF core contains an ARM Cortex-M0 processor that interfaces the analog RF and base-band

circuitries, handles data to and from the system side, and assembles the information bits in a given packet

structure. The RF core offers a high-level, command-based API to the main CPU.

The RF core can autonomously handle the time-critical aspects of the radio protocols (802.15.4 RF4CE

and ZigBee, Bluetooth low energy) thus offloading the main CPU and leaving more resources for the user

application.

The RF core has a dedicated 4-KB SRAM block and runs initially from separate ROM memory. The ARM

Cortex-M0 processor is not programmable by customers.