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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC549 датащи(PDF) 49 Page - Texas Instruments |
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TMS320VC549 датащи(HTML) 49 Page - Texas Instruments |
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49 / 118 page  TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999 49 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Table 13. ’54x Instruction Set Opcodes (Continued) MNEMONIC SYNTAX OPCODE WORDS/ CYCLES† DESCRIPTION MNEMONIC SYNTAX LSB MSB WORDS/ CYCLES† DESCRIPTION CONTROL INSTRUCTIONS B[D] pmad Branch unconditionally with optional delay 2 / 4,2‡ 1111 00Z0 0111 0011 BACC[D] src Branch to address in ACC, optional delay 1 / 6,4‡ 1111 01ZS 1110 0010 BANZ[D] pmad, Sind Branch on AR(ARP) not zero, optional delay 2/4§,2¶,2‡ 0110 11Z0 IAAA AAAA BC[D] pmad, cond [, cond [, cond ] ] Branch conditionally, optional delay 2/5§,3¶,3‡ 1111 10Z0 CCCC CCCC CALA[D] src Call subroutine at address in ACC, optional delay 1/6,4‡ 1111 01ZS 1110 0011 CALL[D] pmad Call unconditionally, optional delay 2 / 4,2¶ 1111 00Z0 0111 0100 CC[D] pmad, cond [, cond [, cond ]] Call conditionally, optional delay 2/5§,3¶,3‡ 1111 10Z1 CCCC CCCC FB[D] extpmad Far branch unconditionally (optional delay) 2 / 4,2‡ 1111 10Z0 1KKK KKKK FBACC[D] src Far branch to address in ACC, optional delay 1 / 6,4‡ 1111 01ZS 1110 0110 FCALA[D] src Far call to address in ACC, optional delay 1 / 6,4‡ 1111 01ZS 1110 0111 FCALL[D] extpmad Far call unconditionally, optional delay 2 / 4,2‡ 1111 10Z1 1KKK KKKK FRAME K Stack pointer immediate offset 1/1 1110 1110 KKKK KKKK FRET[D] Far return (FRETD is for delayed return) 1 / 6,4‡ 1111 01Z0 1110 0100 FRETE[D] Far return, enable interrupts, optional delay 1 / 6,4‡ 1111 01Z0 1110 0101 IDLE K Idle until interrupt 1/4 1111 01NN 1110 0001 INTR K Software interrupt 1/3 1111 0111 110K KKKK MAR Smem Modify auxiliary register 1/1 0110 1101 IAAA AAAA NOP No operation 1/1 1111 0100 1001 0101 POPD Smem Pop top of stack to data memory 1/1 1000 1011 IAAA AAAA POPM MMR Pop top of stack to memory-mapped register 1/1 1000 1010 IAAA AAAA PSHD Smem Push data-memory value onto stack 1/1 0100 1011 IAAA AAAA PSHM MMR Push memory-mapped register onto stack 1/1 0100 1010 IAAA AAAA RC[D] cond [, cond [, cond ]] Return conditionally, optional delay 1/5§,3¶,3‡ 1111 11Z0 CCCC CCCC RESET Software reset 1/3 1111 0111 1110 0000 RET[D] Return, optional delay 1 / 5,3‡ 1111 11Z0 0000 0000 RETE[D] Return and enable interrupts, optional delay 1 / 5,3‡ 1111 01Z0 1110 1011 RETF[D] Return fast and enable interrupts, optional delay 1 / 3,1‡ 1111 01Z0 1001 1011 RPT Smem Repeat next instruction, count is in operand 1/1 0100 0111 IAAA AAAA RPT # K Repeat next instruction, count is short immediate 1/1 1110 1100 KKKK KKKK RPT # lk Repeat next instruction, count is long immediate 2/2 1111 0000 0111 0000 RPTB[D] pmad Block repeat, optional delay 2 / 4,2‡ 1111 00Z0 0111 0010 RPTZ dst, #lk Repeat next instruction and clear accumulator 2/2 1111 000D 0111 0001 RSBX N, SBIT Reset status-register bit 1/1 1111 01N0 1011 SBIT SSBX N, SBIT Set status-register bit 1/1 1111 01N1 1011 SBIT TRAP K Software interrupt 1/3 1111 0100 110K KKKK XC n, cond [, cond [, cond ]] Execute conditionally 1/1 1111 11N1 CCCC CCCC † Values for words and cycles assume the use of DARAM for data. Add one word and one cycle when using long-offset indirect addressing or absolute addressing with a single data-memory operand. ‡ Delayed Instruction § Condition true ¶ Condition false instruction set summary (continued) |
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