TMS320VC549 datasheet(31/118 Pages) TI1

31 / 118 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

serial ports (continued)

Table 3 provides a comparison of the serial ports available in the ’54x devices.

Table 3. Serial Port Configurations for the ’54x

DEVICE

NO. OF STANDARD

SERIAL PORTS

NO. OF BSPs

(BSP ADDRESS RANGES)

NO. OF TDM

SERIAL PORTS

TMS320C541

TMS320LC541

–

TMS320C542

1 (0800h 0FFFh)

TMS320C542

TMS320LC542

–

1 (0800h – 0FFFh)

TMS320LC543

–

1 (0800h – 0FFFh)

TMS320LC545

1 (0800h 0FFFh)

TMS320LC545

TMS320LC545A

1 (0800h – 0FFFh)

–

TMS320LC546

1 (0800h 0FFFh)

TMS320LC546

TMS320LC546A

1 (0800h – 0FFFh)

–

TMS320LC548

–

2 (0800h – 0FFFh

and 1800h – 1FFFh)

TMS320LC549

TMS320VC549

–

2 (0800h – 0FFFh

and 1800h – 1FFFh)

hardware timer

The ’54x devices feature a 16-bit timing circuit with a four-bit prescaler. The timer counter is decremented by

one at every CLKOUT cycle. Each time the counter decrements to zero, a timer interrupt is generated. The timer

can be stopped, restarted, reset, or disabled by specific status bits.

clock generator

The clock generator provides clocks to the ’54x device, and consists of an internal oscillator and a phase-locked

loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided by using a crystal

resonator with the internal oscillator, or from an external clock source. The reference clock input is then either

divided by two (or by four on the ’545A, ’546A, ’548, and ’549) to generate clocks for the ’54x device, or the PLL

circuit can be used to generate the device clock by multiplying the reference clock frequency by a scale factor,

allowing use of a clock source with a lower frequency than that of the CPU.

The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal. When the

PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once

the PLL is locked, it continues to track and maintain synchronization with the input signal. Then, other internal

clock circuitry allows the synthesis of new clock frequencies for use as master clock for the ’54x device.

Two types of PLL are available: a hardware-programmable PLL and a software-programmable PLL. All ’54x

devices have the hardware-programmable PLL except the ’545A, ’546A, ’548, and ’549, which have the

software-programmable PLL. On the hardware-programmable PLL, an external delay must be provided before

the device is released from reset in order for the PLL to achieve lock. With the software-programmable PLL,

a lock timer is provided to implement this delay automatically. Note that both the hardware- and the

software-programmable PLLs require the device to be reset after power up to begin functioning properly.

hardware-programmable PLL

The ’54x can use either the internal oscillator or an external frequency source for an input clock. The clock

generation mode is determined by the CLKMD1, CLKMD2 and CLKMD3 clock mode pins except on the ’545A,

the ’546A, the ’548, and the ’549 (see software-programmable PLL description below). Table 4 outlines the

selection of the clock mode by these pins. Note that both the hardware- and the software-programmable PLLs

require the device to be reset after power up to begin functioning properly.

TMS320VC549 датащи(PDF) 31 Page - Texas Instruments

TMS320VC549 датащи(HTML) 31 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL