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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DS3884AVF датащи(PDF) 4 Page - National Semiconductor (TI) |
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DS3884AVF датащи(HTML) 4 Page - National Semiconductor (TI) |
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4 / 8 page  AC Electrical Characteristics (Note 6) T A = 0˚C to +70˚C, VCC =5V ±10% Symbol Parameter Conditions Min Typ Max Units DRIVER t PHL Dn to Bn Prop. Delay DE* = 0V 135 ns t PLH ( Figure 1, Figure 2 ) 135 ns t PHL DE* to Bn Enable Time Dn = 3V 2 4 6 ns t PLH Disable Time ( Figure 1, Figure 3 ) 246 ns t r Transition Time — Rise/Fall ( Figure 1, Figure 2 ) 1 2 3.5 ns t f 20% to 80% 1 2 3.5 ns SR Skew Rate is Calculated (Note 11) 0.5 V/ns from 1.3V to 1.8V t skew Skew between Drivers in (Note 7) 1 3 ns the Same Package RECEIVER t PHL Bn to Rn Prop. Delay DE* = 3V 245 ns t PLH ( Figure 4, Figure 5 ) 246 ns t skew Skew between Receivers in (Note 7) 1 3 ns Same Package FILTERED RECEIVER t PHL Bn to FRn Prop. Delay PS1 = 0V PS2 = 0V DE* = 3V 6 12 16 ns ( Figure 4, Figure 5 ), R EXT =13 kΩ PS1=0V PS2=3V DE* = 3V 111621 ns ( Figure 4, Figure 5 ), R EXT =13 kΩ PS1=3V PS2=0V DE* = 3V 152127 ns ( Figure 4, Figure 5 ), R EXT =13 kΩ PS1=3V PS2=3V DE* = 3V 253345 ns ( Figure 4, Figure 5 ), R EXT =13 kΩ t PLH Bn to FRn Prop. Delay DE* =3V ( Figure 4, Figure 5 ) (Note 8) 257 ns R EXT =13 kΩ t GR Glitch Rejection PS1 = 0V PS2 = 0V DE* =3V 5 9 16 ns ( Figure 4, Figure 6 ), R EXT =13 kΩ PS1=0V PS2=3V DE* = 3V 101318 ns ( Figure 4, Figure 6 ), R EXT =13 kΩ PS1=3V PS2=0V DE* = 3V 141824 ns ( Figure 4, Figure 6 ), R EXT =13 kΩ PS1=3V PS2=3V DE* = 3V 243142 ns ( Figure 4, Figure 6 ), R EXT =13 kΩ FILTERED RECEIVER TIMING REQUIREMENTS t s PSn to Bn Set-Up Time ( Figure 7 ), R EXT =13 kΩ 250 ns PARAMETERS NOT TESTED Coutput Capacitance at Bn (Note 9) 5 pF t NR Noise Rejection (Note 10) 1 ns Note 6: Input waveforms shall have a rise/fall time of 3 ns. Note 7: tskew is an absolute value defined as differences seen in propagation delays between drivers in the same package with identical load conditions. Note 8: Filtered receiver tPLH is independent of filter setting. Note 9: The parameter is tested using TDR techniques described in P1194.0 BTL Backplane Design Guide. Note 10: This parameter is tested during device characterization. The measurements revealed that the part will reject 1 ns pulse width. Note 11: Futurebus+ transceivers are required to limit bus signal rise and fall times to no faster than 0.5V/ns, measured between 1.3V and 1.8V (approximately 20% to 80% of nominal voltage swing). The rise and fall times are measured with a transceiver loading equivalent to 12.5 Ω tied to +2.1V DC. www.national.com 4 |
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