| поискавой системы для электроныых деталей |
|
DS3875 датащи(PDF) 23 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
DS3875 датащи(HTML) 23 Page - National Semiconductor (TI) |
|
23 / 58 page ![]() 50 Arbitrating for Futurebusa (Continued) When a message is received the FIFO strobe (FSTR ) will be negated strobing a new message into the external FIFO given the following conditions 1 The message is not being sent by this module 2 This is the second pass of an arbitration message 3 No errors occurred during this arbitration cycle 4 This is not a powerfail interrupt message ( PFINT ) Once all the modules have negated AQ upon receiving AQI the arbitration cycle will transition to Phase 0 TLH10747 – 16 FIGURE 7a DS3875 Phase 0 Arbitration State Diagram Note HALT is assumed to be negated in this state diagram Also the arbitration Controller GO bit in CTRL3 register must be asserted for the controller to accept requests Otherwise this module may not compete but will be a by-stander Note 1 Idle Bus Arbritation during Phase 0 is not an internal state of the Arbitration Controller It is shown in this state diagram only to give a better understanding of Phase 0 arbitration Note 2 The Arbitration Controller does not check for LKD but it should not be asserted during IBA to be in compliance with the Futurebusa specification If lock was asserted during IBA another module could win IBA and try to access this modules locked resources this would result in deadlock Also the Arbitration controller does not check AS DS DI this is left up to external logic and this must be the first pass if two pass arbitration has been selected Note 3 The output di from this module is driven from external control logic it is only shown in this diagram to allow a clearer understanding of how IBA relates to normal arbitration Note 4 Note that message request (MGRQ ) has a higher priority inside the arbitration controller then does bus request (BRQ ) Note 5 This is a dummy arbitration cycle initiated to unlock (UNLK ) the modules resources The dummy cycle is initiated by the current master if the modules resources are still locked ( LKD ) after end of tenure (ENDT ) has been issued ( BGRNT MasterLKD ENDT ) and the arbitration bus is idle Note 6 If this is the second pass of a two-pass arbitration cycle and a new request ( BRQ or MGRQ ) is generated that request will not be allowed to compete until the next arbitration cycle Note that pre-emption is allowed Note 7 If Two-Pass arbitration has been selected Parking is only possible during Phase 0 of the first pass 23 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |