DS3875 datasheet(37/58 Pages) NSC

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70 Register Description (Continued)

78 STATE

(ADD(30) e 0110)

This register contains the present state of the arbitration controller This information may be used for testing and debugging

purposes Defaults to h 01

76543210

ST5

ST4

ST3

ST2

ST1

ST0

Bit

Symbol

Description

0 – 5

ST(05)

These bits indicate the current phase of the arbitration controller

79 STATUS

(ADD(30) e 0111)

This register contains status information and internal counterdivider test bits The M C W bits default to zero The counter test

bits may be evaluated when feeding in a test clock

76543210

CT2

CT1

CT0

Bit

Symbol

Description

2 – 4

CT(02)

Counter test bits

CT2set to one when 1 ms timeout occurs

CT1set to one when divide by 40 divider has divided 40 times

CT0set to one when divide by n divider has divided n times

Win attribute of the module A ‘‘one’’ indicates that the module is the winner of the current

arbitration cyclepass

Competitor attribute of the module A ‘‘one’’ indicates that the module is competing for the bus

Master attribute of the module A ‘‘one’’ indicates that the module is the current master of the

bus

710 RXCN0

(ADD(30) e 1000)

This register stores the received pass 1 arbitration number of a two pass number (CN e 0) Defaults to h 00

543210

0P7P6P5P4P3P2P1

Bit

Symbol

Description

0 – 6

P(17)

Priority field of the current mastermaster elect arbitration number This register is used only if

the controller is configured to arbitrate in Unrestricted two pass mode

This field is fixed at zero as specified in the Futurebusa spec for the pass 1 number of a two

pass arbitration

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