DS3875 datasheet(39/58 Pages) NSC

39 / 58 page

70 Register Description (Continued)

716 REV NO

(ADD(30) e 1111)

Revision number of the controller

76543210

Bit

Symbol

Description

0 – 7

R(07)

REV NO

80 Programming Registers

During power up

the registers should be initially pro-

grammed The host may readwrite tofrom the register

block at any time The host may select to write data into the

ing edge of CS

A zero on the SEL input pin configures the

controller to latch in data on the falling edge of DSACK

while a one sets the controller to latch in data on the rising

edge of CS

Refer to the timing diagrams (see

Figures T2a

b c )

81 HOST WRITE CYCLE USING FALLING EDGE OF

DSACK

(Figure T2A)

1 R

W signal is negated

ADD(30) contains the address of the register to be ac-

cessed (Note The setup time with respect to CS must

be satisfied)

2 CS is asserted ( CS )

3 When the proper setup time of CS to the rising edge of

clock is met and CS is low for at least 3 clock cycles

then DATA(70) will be latched into the register by the

falling edge of DSACK

on the 3rd rising clock edge

after the assertion of CS

If the CS setup time is not

met and CS

is low for at least 3 clock cycles then

DSACK is asserted and the data (DATA(70)) is latched

into the arbitration register on the following 3rd or 4th

rising clock edge after the assertion of CS

IfCS

negated (CS ) before 3 clock cycles then DSACK

not generated and as a default DATA (70) is latched

into the arbitration controller register on the rising edge

of CS

4 Host negates CS

5 Arbitration Controller negates DSACK

(DSACK )ifit

was asserted

82 HOST WRITE CYCLE USING RISING EDGE OF CS

(Figure T2b)

1 R

W signal is negated

ADD(30) contains the address of the register to be ac-

cessed (Note The setup time with respect to CS must

be satisfied)

2 CS is asserted ( CS )

3 DSACK is asserted ( DSACK ) by the Arbitration Con-

troller when CS is asserted for at least three clock cy-

cles If CS is negated (CS ) before three clock cycles

DSACK

is not asserted The DSACK

signal may be

used or ignored by the system designer in this case

4 Host negates CS

DATA (70) which satisfied the setup

time to the rising edge of CS is latched into the arbitra-

tion controller register

5 Arbitration Controller negates DSACK

(DSACK )ifit

was asserted

83 HOST READ CYCLE

(Figure T2c)

1 R

W signal is set high

ADD (30) contains the address of the register to be ac-

cessed (Note The setup time with respect to CS must

be satisfied)

2 CS is asserted ( CS )

3 The data will be available on the DATA (70) bus within

the access time specified in the AC timing section

4 The Data Strobe ACKnowledge (DSACK ) signal is gen-

erated as an acknowledge to the host signifying the va-

lidity of the accessed data DSACK may be used to in-

sert WAIT states to the host during a host read cycle

When the proper setup time of CS to the rising edge of

clock is met and CS is low for at least three clock cy-

cles DSACK is asserted ( DSACK ) on the 3rd rising

clock edge after the assertion of CS

If the CS setup

time was not met and CS is low for at least three clock

cycles then DSACK is asserted on the following 3rd or

4th rising clock edge after the assertion of CS

IfCS is

not low for at least 3 clock cycles DSACK is not gener-

ated

5 Host reads data and negates CS (CS )

6 Arbitration Controller negates DSACK

(DSACK )ifit

was asserted

90 ClockTimerDelay Lines

(See

Figure 9 ) The input clock signal (CLK) to the arbitra-

tion controller is assumed to be a clock from 2 MHz to 40

MHz in steps of 1 MHz

The clock signal is also used for synchronization purposes

during read or write transfers This is accomplished by syn-

chronizing the DSACK (Data Strobe Acknowledge) output

from the Arbitration Controller to the clock during arbitration

controller register reads or writes

The binary value of the input clock (CLK) frequency is load-

ed into the CTRL1 50 register This value is used to pro-

gram the divide by n counter to scale the input clock down

to a 1 MHz clock internally The PLL ring oscillator also has

a clock divider (divide by 40) to scale it down toa1MHz

clock These two clocks are compared and the difference

between the two clocks is fed back to the ring oscillator to

cause it to lock onto the appropriate frequency

The PLL is used to generate several programmable delay

lines and the 1 ms Timer used during phase 2 and phase 4

The 1 ms timer divide by 40 divider and divide by n divider

can be tested to determine proper functionality Refer to

Testing the Arbitration Controller and Register Description

sections for details

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