DS3875 datasheet(7/58 Pages) NSC

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20 Introduction to Futurebusa

Arbitration (Continued)

21 THE ARBITRATION STATES

Figure 1 is an Arbitration State Diagram showing four states

that a module may enter as well as the events that cause

the module to change states during the arbitration process

Transitions from one state to another occur only when cer-

tain conditions are met based on the arbitration phase and

the arbitration bus lines Once a control acquisition cycle

has started all modules must participate in the arbitration to

remain synchronized within the system

TLH10747 – 3

FIGURE 1

30 Introduction to DS3875

Arbitration Controller

The DS3875 Arbitration Controller implements the complete

requirements fo the IEEE 8961 specifications For example

both arbitration modes of operation (Unrestricted and Re-

stricted) are supported Also either Idle Bus Arbitration or

Parking may be selected for cases when only one request

or no request for bus competition exist The controller is

software configurable to operate as a slowfast module

This selects the minimum time the arbitration controller

must wait during the arbitration competition before it can

read the resulting competition status This delay allows arbi-

tration competition lines (AB 7

ABP ) to settle due

to several arbitration numbers being applied to them (Wire-

ored bus lines) Further a built-in PLL which accepts a

clock signal from 2 MHz to 40 MHz in steps of 1 MHz

controls several programmable delay lines used for releas-

ing ar

after issuing CMPT

IBA

CMPT

(PS(10)) This

delay compensates for the chip to chip skew to ensure suffi-

cient time to drive the arbitration competition number onto

the arbitration competition lines during normal arbitration or

to assert the ADDATA lines during Idle Bus Arbitration be-

fore releasing ar

Internally the PLL also generates the 1

s timer used during arbitration phase 2 and phase 4

The Arbitration Controller supports Arbitration message

sending A FIFO strobe FSTR

is provided to store more

than one arbitration message externally to prevent overrun

Also a hardwired register contains the first word of the arbi-

tration message (h 1ff) Additional registers which hold arbi-

tration numbers status information controller configuration

information and an arbitration message can be accessed

by the host through ReadWrite operations For outgoing

arbitration numbers the on chip parity generator unloads

the host of the parity generation function For incoming arbi-

tration numbers the DS3885 Arbitration Transceiver per-

forms the parity check function and drives the PER input

signal to the Controller Separate interrupt pins for error oc-

currence reception of an arbitration message and recep-

tion of Powerfail message are available These interrupts

are cleared by performing a dummy write cycle to these

registers

31 DS3875 Futurebusa Arbitration Controller (Distrib-

uted) Configuration for IEEE 8961 Compliance

The DS3875 Futurebusa Arbitration Controller implements

the complete requirements of the IEEE 8961 specification

On chip reset (RST ) the arbiter defaults to the 8961 com-

pliance configuration features

The D53875 Distributed Arbiter was designed before the

8961 specification was finalized Thus it contains additional

options that can he selected in proprietary bus applications

or 8961 compatible bus applications There are three fea-

tures in total that can be chosen through register program-

ming

First an explanation of each feature will be given so that if

an application can take advantage of the option it can be

programmed Then the 8961 compliance configuration is

given so the arbiter will operate in complete accordance

with the specification

Arbitration Number UnrestrictedRestricted Mode

In Distributed Arbitration both priority and fairness protocols

are implemented Applications requiring quick access to the

Futurebusa backplane can be assigned high priority to re-

duce bus latency times Applications with the same (equal)

need of the backplane bus a fairness protocol is guaran-

teed Thus distributed arbitration implements a fairness pro-

tocol for modules assigned the same priority classification

The arbitration competition number encodes this informa-

tion onto eight lines AB 70 and arbitration number line

ABP The Arbitration competition number consists of three

fields priority round robin and geographical address Dis-

tributed Arbitration protocol allows from 1 to 256 priority lev-

els Systems not requiring more then two priority levels a

single pass competition number will suffice one bit for prior-

ity Systems with greater then two priority levels implement-

ed will need a two pass competition number where eight

bits are allocated for priority representation Now the com-

petition number exactly contains 5 bits for geographical ad-

dress (this guarantees uniqueness) 1 bit for round robin

either 1 bit for priority (single pass) or 8 bits for priority (two

pass) and 1 bit to designate if the number is single pass or

two pass (Refer to Table II on page 14)

When the DS3875 was designed two modes of operation

were defined Unrestricted and Restricted The Unrestricted

mode allowed one and two pass competition numbers to

coexist in a system The Restricted mode allowed only one

pass competition numbers Now the 8961 specification

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