LP8545 datasheet(16/44 Pages) TI1

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LP8545

SNVS635D – APRIL 2010 – REVISED DECEMBER 2013

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Resolution Selector

Resolution selector takes the necessary MSB bits from the input data to match the output resolution. For

example if 11-bit resolution is used for output, then 11 MSB bits are selected from the input. Dither bits are not

taken into account for the output resolution. This is to make sure that in steady state condition, there is no

dithering used for the output.

Sloper

Sloper makes the smooth transition from one brightness value to another. Slope time can be adjusted from 0 to

500 ms with <SLOPE[3:0]> EEPROM bits. The sloper output is 16-bit value.

Dither

With dithering the output resolution can be “artificially” increased during sloping from one brightness value to

another. This way the brightness change steps are not visible to eye. Dithering can be from 0 to 3 bits, and is

selected with <DITHER[1:0]> EEPROM bits.

PWM Comparator

The PWM counter clocks the PWM comparator based on the duty cycle value received from Dither block. Output

of the PWM comparator controls directly the LED drivers. If PSPWM mode is used, then the signal to each LED

output is delayed certain amount.

Current Setting

Maximum current of the LED outputs is controlled with CURRENT[7:0] EEPROM register bits linearly from 0 to

30 mA. If EN_I_RES = 1 the maximum LED output current can be scaled also with external resistor, RISET. RISET

controls the LED current as follows:

•

Default value for CURRENT[7:0] = 7Fh (127d).

(1)

Therefore the output current can be calculated as follows:

Note: formula is only approximation for the actual current.

•

E.g. If 16 k

Ω RISET resistor is used, then the LED maximum current is 23 mA.

(2)

PWM Frequency Setting

PWM frequency is selected with PWM_FREQ[4:0] EEPROM register. If PLL clock frequency multiplication is

used, it will effect to the output PWM frequency as well. <PWM_RESOLUTION[1:0]> EEPROM bits will select the

PLL output frequency and hence the PWM frequency and resolution. Below are listed PWM frequencies with

<EN_VSYNC]> = 0. PWM resolution setting affects the PLL clock frequency (5 MHz…40 MHz). Highlighted

frequencies with boldface can be selected also with external resistor RFSET. To activate RFSET frequency selection

the <EN_F_RES> EEPROM bit must be 1.

PWM_RES[1:0]

PWM FREQ[4:0]

5 MHz

10 MHz

20 MHz

40 MHz

Resolution (bits)

11111

19232

11110

16828

11101

14424

11100

12020

11011

9616

19232

11010

7963

15927

11001

6386

12771

11000

4808

9616

19232

10111

4658

9316

18631

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