LP8545 datasheet(14/44 Pages) TI1

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5MHz internal

oscillator

PLL[12:0]

PWM generation

PWM_FREQ[4:0]

or External

set resistor RFSET

VBOOST

LED Drivers 1-6

Divider

1/N

5 MHz...40 MHz

PSPWM 0/1

Boost

Filter

VCO

Counter

1/N

PLL

VSYNC

60 Hz

EN_VSYNC

Phase

Detector

State machine,

PWM input, internal

timings, Slope etc.

BOOST_FREQ

N = 4, 8, 16, 32

PWM_RESOLUTION[1:0]

BOOST

LED

DRIVERS

LOGIC

EEPROM

C /

INTERFACE

LDO

OSC

TSD

PWM

DETECTOR

VLDO

GND

GND_SW

GND_LED

PWM

VDDIO

SCLK

SDA

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

PLL

FAULT

VIN

TEMP

SENSOR

MCU

VIN

FILTER

VSYNC

ISET

FSET

RISET

RFSET

LP8545

SNVS635D – APRIL 2010 – REVISED DECEMBER 2013

www.ti.com

Block Diagram

Clock Generation

LP8545 has internal 5 MHz oscillator which is used for clocking the boost converter, state machine, PWM input

duty cycle measurement, internal timings such as slope time for output brightness changes.

Internal clock can be used for generating the PWM output frequency. In this case the 5 MHz clock can be

multiplied with the internal PLL to achieve higher resolution. The higher the clock frequency for PWM generation

block, the higher the resolution but the tradeoff is higher IQ of the part. Clock multiplication is set with

<PWM_RESOLUTION[1:0]> EEPROM Bits.

The PLL can also be used for generating the required PWM generation clock from the VSYNC signal. This makes

sure that the LED output PWM is always synchronized to the VSYNC signal and there is no clock variation

between LCD display video update and the LED backlight output frequency. Also HSYNC signal up to 55 kHz can

be used.

PLL has internal counter which has 13-bit control <PLL[12:0]> to achieve correct output clock frequency based

on the VSYNC frequency.

For the PLL it can take couple of seconds to synchronize to 60 Hz VSYNC signal in startup and before this correct

PWM clock frequency is generated from internal oscillator. FILTER pin component selection affects the time it

takes from the PLL to lock to VSYNC signal. When backlight is turned off the EN pin must be set low to ensure

correct PLL behavior during next startup.

Figure 12. Principle of the Clock Generation

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