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LP8545 датащи(PDF) 9 Page - Texas Instruments |
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LP8545 датащи(HTML) 9 Page - Texas Instruments |
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9 / 44 page ![]() LP8545 www.ti.com SNVS635D – APRIL 2010 – REVISED DECEMBER 2013 I 2C SERIAL BUS TIMING PARAMETERS (SDA, SCLK) (1) Limit Symbol Parameter Units Min Max fSCLK Clock Frequency 400 kHz 1 Hold Time (repeated) START Condition 0.6 µs 2 Clock Low Time 1.3 µs 3 Clock High Time 600 ns 4 Setup Time for a Repeated START Condition 600 ns 5 Data Hold Time 50 ns 6 Data Setup Time 100 ns 7 Rise Time of SDA and SCL 20+0.1Cb 300 ns 8 Fall Time of SDA and SCL 15+0.1Cb 300 ns 9 Set-up Time for STOP condition 600 ns 10 Bus Free Time between a STOP and a START Condition 1.3 µs Capacitive Load Parameter for Each Bus Line Cb 10 200 ns Load of 1 pF corresponds to 1 ns. (1) Ensured by design. VDDIO = 1.65V to 5.5V. Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: LP8545 |
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