LP5550

SNVS378G – OCTOBER 2005 – REVISED APRIL 2013

www.ti.com

Operating Ratings

(1) (2)

VBAT1, VBAT2, VBATSW

3.0V to 5.5V

−40°C to +125°C

(3)

−40°C to +85°C

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits

and associated test conditions, see the Electrical Characteristics tables.

(2)

All voltages are with respect to the potential at the GND pin.

(3)

In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-

OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance

of the part/package in the application (

Thermal Properties

(4)

Junction-to-Ambient Thermal Resistance (

39.8°C/W

(4)

Junction-to-ambient thermal resistance (

θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set

forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102mm x 76mm x 1.6mm with a 2x1 array of

thermal vias. The ground plane on the board is 50mm x 50mm. Thickness of copper layers are 36µm/18µm/18µm/36µm

(1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W.Junction-to-ambient thermal

resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care

must be paid to thermal dissipation issues in board design.The value of

material, layout, and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT),

special care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application Note AN-1187:

Leadless Leadframe Package (LLP) (SNOA401) and the Power Efficiency and Power Dissipation section of this datasheet.

General Electrical Characteristics

= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C

(1) (2) (3)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Shutdown Supply current

1

6

µA

Sleep State Supply Current

70

85

µA

on. All other circuits off.

Acitve State Supply Current

140

165

µA

(No load, PFM mode)

Switcher on, PWI on.

Thermal Shutdown Threshold

160

°C

Thermal Shutdown Hysteresis

10

(1)

All voltages are with respect to the potential at the GND pin.

(2)

Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the

most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control.

(3)

Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics

LDO1 (PLL/Fixed Voltage) Characteristics

= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C

(1) (2) (3)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

1mA

Output Voltage Accuracy

-3%

1.2

3%

V

3.0V

Programmable Output Voltage

0µA

0.7

1.2

2.2

V

Range

Programming Resolution = 100mV

Recommended Output Current

3.0V

≤ VBAT1,2,SW ≤ 5.5V

100

mA

Short Circuit Current Limit

350

Quiescent Current

(4)

35

45

µA

(1)

All voltages are with respect to the potential at the GND pin.

(2)

Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the

most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control.

(3)

Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics

(4)

Quiescent current for LDO1, LDO2, and LDO3 do not include shared functional blocks such as the bandgap reference.

4

Submit Documentation Feedback

Copyright © 2005–2013, Texas Instruments Incorporated

Product Folder Links: LP5550