LP5550

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SNVS378G – OCTOBER 2005 – REVISED APRIL 2013

Pin Descriptions (continued)

Pin No.

Name

I/O

Type

Description

9

VBATSW

P

P

Battery supply voltage for switching regulator

10

SW

O

A

Switcher pin connected to coil

11

SWGND

G

G

Switcher ground

12

VBAT2

P

P

Battery supply voltage

13

VO3

O

A

LDO3 output, on-chip memory supply voltage

14

VFB

I

A

Switcher output voltage for supplying SoC core logic

15

AGND

G

G

Analog Ground

16

ENABLE

I

D

Enable, active high

A: Analog Pin

D: Digital Pin

I: Input Pin

O: Output Pin

I/O: Input/Output Pin

P: Power Pin

G: Ground Pin

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1) (2) (3) (4)

VBAT1, VBAT2, VBATSW

-0.3 to +6.0V

VO1, VO2, VO3 to GND

-0.3 to +VBAT1+0.3V

ENABLE, RESETN, VFB, SW, SPWI, SCLK, PWROK

-0.3 to VBAT2+0.3V

DGND, AGND, SWGND to GND SLUG

±0.3V

Junction Temperature (TJ-MAX)

150°C

Storage Temperature Range

-65°C to 150°C

1.0 W

Maximum Lead Temperature (Soldering)

Human Body Model

All pins

2.0kV

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits

and associated test conditions, see the Electrical Characteristics tables.

(2)

All voltages are with respect to the potential at the GND pin.

(3)

If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(4)

For detailed soldering specifications and information, please refer to Application Note AN-1187 : Leadless Leadframe Package (LLP)

(SNOA401).

(5)

The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated

using the formula P = (TJ – TA)/

ambient thermal resistance. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications

where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.Internal thermal

shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=150°C (typ.) and disengages at

TJ=140°C (typ.).

(6)

The Human body model is a 100 pF capacitor discharged through a 1.5 k

Ω resistor into each pin.

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