LP3936SLSLASHNOPB datasheet(5/30 Pages) TI1

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LP3936

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SNVS259D – NOVEMBER 2003 – REVISED MAY 2013

Electrical Characteristics

(1) (2)

Limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the operating ambient temperature range

(

−40°C ≤ TA ≤ +85°C). Unless otherwise noted, specifications apply to the Block Diagram with: VDD1 = VDD2 = VDD_IO = 3.6V,

CVDD1, CVDD2, CVDDIO = 1 µF, CIN, COUT = 10 µF, CVDDA = 1 µF, CVREF = 0.1 µF, LBOOST = 10 µH

(3).

Symbol

Parameter

Condition

Min

Typ

Max

Units

VDD1,2

Supply Voltage

3.0

3.6

6.0

IDD

Standby Supply Current

NSTBY = L (register)

µA

(VDD1 and VDD2 current)

CS, SCL, DI, NRST = H

VDD1, VDD2 = 3.6V

No-Load Supply Current

NSTBY = H (reg.)

170

300

µA

(VDD1 and VDD2 current, boost off)

EN_BOOST = L (reg.)

SCL, CS, DI, NRST = H

Full Load Supply Current

NSTBY = H (register)

(VDD1 and VDD2 current, boost on)

NRST, CS, SCL, DI = H

RGB_EN = L

WLED1 … 6 = L

EN_AMBADC = L

IDD_IO

VDD_IO Standby Supply Current

NSTBY = L (register)

µA

CS, SCL, DI, NRST = H

VDD_IO Operating Supply Current

1 MHz Clock Frequency

µA

CL = 50 pF at DO pin

VREF

Reference Voltage (4)

IREF ≤ 1 nA,

1.205

1.23

1.255

Test Purposes Only

−2

VDDA

LDO Output Voltage

IVDDA < 1 µA

2.688

2.8

2.912

% V

–4

(1)

All voltages are with respect to the potential at the GND pins (GND1, GND2, GND_T, GND_BOOST, GND_WLED, GND_RGB).

(2)

Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.

(3)

Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.

(4)

VREF pin (Bandgap reference output) is for internal use only. A capacitor should always be placed between VREF and GND1.

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