Philips Semiconductors

Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22

34

X1/CLK

A1–A4

RWN

CSN

D0–D7

DTACKN

tCSC

tAS

tCS

tDF

tDAT

tDAH

tCH

tRWD

tDD

tDCR

tAH

DATA VALID

NOT

VALID

tDA

NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.

SD00687

Figure 6. Bus Timing (Read Cycle) (68XXX mode)

X1/CLK

A1–A4

RWN

CSN

D0–D7

DTACKN

tCSC

tAS

tCS

tDH

tDAT

tDAH

tCH

tRWD

tDS

tDCW

tAH

NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.

SD00688

Figure 7. Bus Timing (Write Cycle) (68XXX mode)

NOTE:

For Figures 6 and 7 WRN changing within the time of CEN low may cause short read or write pulses that could upset internal pointers and

registers. Bus action terminates on the rise of CEN or the fall of DACKN, which ever occurs first.