SC28L91 datasheet(22/42 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22

MR0 – Mode Register 0

Mode Register 0. MR0 is accessed by setting the MR pointer to 0 via the command register command B.

Addr

Bit 7

BIT 6

BITS 5:4

BIT 3

BIT 2

BIT 1

BIT 0

MR0

WATCHDOG

RxINT BIT 2

TxINT (1:0)

FIFO SIZE

BAUD RATE

EXTENDED II

TEST 2

BAUD RATE

EXTENDED 1

0x00

0x08

0 = Disable

1 = Enable

See Tables in

MR0 descrip-

tion

See Table 4

0 = 8 byte FIFO

1 = 16 byte FIFO

0 = Normal

1 = Extend II

Set to 0

0 = Normal

1 = Extend

MR0[7]—Watchdog Control

This bit controls the receiver watchdog timer. 0 = disable,

1 = enable. When enabled, the watch dog timer will generate a

receiver interrupt if the receiver FIFO has not been accessed within

64 bit times of the receiver 1X clock. This is used to alert the control

processor that data is in the RxFIFO that has not been read. This

situation may occur when the byte count of the last part of a

message is not large enough to generate an interrupt.

MR0[6]—Rx Interrupt bit 2

Bit 2 of receiver FIFO interrupt level. This bit along with Bit 6 of MR1

sets the fill level of the FIFO that generates the receiver interrupt.

MR0[6], MR1[6] Rx Interrupt bits

Note that this control is split between MR0 and MR1. This is for

backward compatibility to legacy software of the SC2692 and

SCN2681 dual UART devices.

Table 3. Receiver FIFO

Interrupt fill level (MR0(3) = 0 (8 bytes)

MR0[6] MR1[6]

Interrupt Condition

1 or more bytes in FIFO (Rx RDY)

6 or more bytes in FIFO

4 or more bytes in FIFO

8 bytes in FIFO (Rx FULL)

Table 3a. Receiver FIFO

Interrupt fill level(MR0(3)=1 (16 bytes)

MR0[6] MR1[6]

Interrupt Condition

1 or more bytes in FIFO (Rx RDY)

8 or more bytes in FIFO

12 or more bytes in FIFO

16 bytes in FIFO (Rx FULL)

For the receiver these bits control the number of FIFO positions

filled when the receiver will attempt to interrupt. After the reset the

receiver FIFO is empty. The default setting of these bits cause the

receiver to attempt to interrupt when it has one or more bytes in it.

MR0[5:4]—Tx interrupt fill level.

Table 4. Transmitter FIFO

Interrupt fill level MR0(3) = 0 (8 bytes)

MR0[5:4]

Interrupt Condition

8 bytes empty (Tx EMPTY)

4 or more bytes empty

6 or more bytes empty

1 or more bytes empty (Tx RDY)

Table 4a. Transmitter FIFO

Interrupt fill level MR0(3) = 1 (16 bytes)

MR0[5:4]

Interrupt Condition

16 bytes empty (Tx EMPTY)

8 or more bytes empty

12 or more bytes empty

1 or more bytes empty (Tx RDY)

For the transmitter these bits control the number of FIFO positions

empty when the transmitter will attempt to interrupt. After the reset

the transmit FIFO has 8 bytes empty. It will then attempt to interrupt

as soon as the transmitter is enabled. The default setting of the MR0

bits [5:4] condition the transmitter to attempt to interrupt only when it

is completely empty. As soon as one–byte is loaded, it is no longer

empty and hence will withdraw its interrupt request.

MR0[3]—FIFO size

Selects the FIFO depth at 8 or 16 bytes. See Tables 3 and 4

MR0[2:0]—Baud Rate Group Selection

These bits are used to select one of the six–baud rate groups.

See Table 5 for the group organization.

• 000 Normal mode

• 001 Extended mode I

• 100 Extended mode II

Other combinations of MR2[2:0] should not be used.

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