SC28L91 datasheet(17/42 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22

This continues regardless of issuance of the stop counter command.

ISR[3] is reset by the stop counter command.

NOTE: Reading of the CTU and CTL registers in the timer mode is

not meaningful. When the C/T is used to generate a baud rate and

the C/T is selected through the CSR then the receiver and/or

transmitter will be operating in the 16x mode. Calculation for the

number ‘n’ to program the counter timer upper and lower registers is

shown below.

c tclock rate

2 * 16 * Baud rate

Often this division will result in a non-integer number; 26.3 for

example. One can only program integer numbers to a digital divider.

Therefore 26 would be chosen. This gives a baud rate error of

0.3/26.3 which is 1.14%; well within the ability of the asynchronous

mode of operation.

Counter Mode

In the counter mode the counter/timer counts the value of the CTLR

CTUR down to zero and then sets the ISR[3] bit and sets the

counter/timer output from 1 to 0. It then rolls over to 65,365 and

continues counting with no further observable effect. Reading the

C/T in the counter mode outputs the present state of the C/T. If the

C/T is not stopped, a read of the C/T may result in changing data on

the data bus.

Timeout Mode

The timeout mode uses the received data stream to control the

counter. The time-out mode forces the C/T into the timer mode.

Each time a received character is transferred from the shift register

to the RxFIFO, the counter is restarted. If a new character is not

received before the counter reaches zero count, the counter ready

bit is set, and an interrupt can be generated. This mode can be used

to indicate when data has been left in the Rx FIFO for more than the

programmed time limit. If the receiver has been programmed to

interrupt the CPU when the receive FIFO is full, and the message

ends before the FIFO is full, the CPU will not be interrupted for the

remaining characters in the RxFIFO.

By programming the C/T such that it would time out in just over one

character time, the above situation could be avoided. The processor

would be interrupted any time the data stream had stopped for more

than one character time. NOTE: This is very similar to the watch dog

timer of MR0. The difference is in the programmability of the delay

timer and that this indicates that the data stream has stopped. The

watchdog timer is more of an indicator that data is in the FIFO is not

enough to cause an interrupt. The watchdog is restarted by either a

receiver load to the RxFIFO or a system read from it.

This mode is enabled by writing the appropriate command to the

command register. Writing an ‘0xAn’ to CR will invoke the timeout

mode for that channel. Writing a ‘Cx’ to CR will disable the timeout

mode. The timeout mode disables the regular START/STOP counter

commands and puts the C/T into counter mode under the control of

the received data stream. Each time a received character is

transferred from the shift register to the RxFIFO, the C/T is stopped

after one C/T clock, reloaded with the value in CTUR and CTLR and

then restarted on the next C/T clock. If the C/T is allowed to end the

count before a new character has been received, the counter ready

Bit, ISR[3], will be set. If IMR [3] is set, this will generate an interrupt.

Since receiving a character restarts the C/T, the receipt of a

character after the C/T has timed out will clear the counter ready bit,

ISR [3], and the interrupt. Invoking the ‘Set Timeout Mode On’

command, CRx = 0xAn, will also clear the counter ready bit and stop

the counter until the next character is received. The counter timer is

controlled with six commands: Start/Stop C/T, Read/Write

Counter/Timer lower register and Read/Write Counter/Timer upper

mode of operation. Please see the detail of the commands under the

CTLR CTUR Register descriptions.

Time Out Mode Caution

When operating in the special time out mode it is possible to

generate what appears to be a “false interrupt”, i.e. an interrupt

without a cause. This may result when a time-out interrupt occurs

and then, BEFORE the interrupt is serviced, another character is

received, i.e., the data stream has started again. (The interrupt

latency is longer than the pause in the data stream.) In this case,

when a new character has been receiver, the counter/timer will be

restarted by the receiver, thereby withdrawing its interrupt. If, at this

time, the interrupt service begins for the previously seen interrupt, a

read of the ISR will show the “Counter Ready” bit not set. If nothing

else is interrupting, this read of the ISR will return a x’00 character.

This action may present the appearance of a spurious interrupt.

Communications

The communications channel of the SC28L91 comprises a

full-duplex asynchronous receiver/transmitter (UART). The operating

frequency for the receiver and transmitter can be selected

independently from the baud rate generator, the counter/timer, or

from an external input. The transmitter accepts parallel data from the

CPU, converts it to a serial bit stream, inserts the appropriate start,

stop, and optional parity bits and outputs a composite serial stream

of data on the TxD output pin. The receiver accepts serial data on

the RxD pin, converts this serial input to parallel format, checks for

start bit, stop bit, parity bit (if any), or break condition and sends an

assembled character to the CPU via the receive FIFO. Three status

bits (Break Received, Framing and Parity Errors) are also FIFOed

with the data character.

Input Port

The inputs to this unlatched 7-bit (6-bit for 68xxx mode) port can be

read by the CPU by performing a read operation at address 0xD. A

High input results in a logic 1 while a Low input results in a logic 0.

D7 will always read as a logic 1. The pins of this port can also serve

as auxiliary inputs to certain portions of the UART logic, modem and

DMA.

Four change-of-state detectors are provided which are associated

with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High

transition of these inputs, lasting longer than 25–50

∝s, will set the

corresponding bit in the input port change register. The bits are

cleared when the register is read by the CPU. Any change-of-state

can also be programmed to generate an interrupt to the CPU.

The input port change of state detection circuitry uses a 38.4 kHz

sampling clock derived from one of the baud rate generator taps.

This results in a sampling period of slightly more than 25

∝s (this

assumes that the clock input is 3.6864 MHz). The detection circuitry,

in order to guarantee that a true change in level has occurred,

requires two successive samples at the new logic level be observed.

As a consequence, the minimum duration of the signal change is

∝s if the transition occurs “coincident with the first sample pulse”.

The 50

∝s time refers to the situation in which the change-of-state is

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