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LM5134

SNVS808C – MAY 2012 – REVISED FEBRURARY 2016

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The speed at which the drain node rises during turnoff is typically dictated by the current in the inductor at

turnoff, and thus is not dependent on the turnoff current of the drive circuit. However, depending on the amount

of current flowing through the drain to gate capacitance of the MOSFET as the drain voltage rises and the

impedance to ground of the drive circuit, it is possible for the gate voltage to exceed the threshold voltage of the

FET and turn the FET back on, known as a false turnon.

For these reasons, turn the FET off as fast as possible. The LM5134 allows the flexibility of different turnon and

turnoff speeds, and avoids false turnon by providing a pilot output to drive a small pulldown MosFET, which can

be placed close to the main FET and reduces the impedance from gate to ground on turnoff.

Using the example of a power MOSFET, the system requirement for the switching speed is typically described in

terms of the slew rate of the drain-to-source voltage of the power MOSFET (such as dV/dt). For example, the

system requirement might state that a SPP20N60C3 power MOSFET must be turned on with a dV/dt of 20 V/ns

or higher, under a DC bus voltage of 400 V in a continuous-conduction-mode (CCM) boost PFC converter

application. This type of application is an inductive hard-switching application, and reducing switching power

losses is critical. This requirement means that the entire drain-to-source voltage swing during power MOSFET

turnon event (from 400 V in the OFF state to V DS(on) in on state) must be completed in approximately 20 ns or

less. When the drain-to-source voltage swing occurs, the Miller charge of the power MOSFET (QGD parameter

in SPP20N60C3 power MOSFET data sheet = 33 nC typical) is supplied by the peak current of gate driver.

According to the power MOSFET inductive switching mechanism, the gate-to-source voltage of the power

MOSFET at this time is the Miller plateau voltage, which is typically a few volts higher than the threshold voltage

of the power MOSFET, VGS(TH). To achieve the targeted dV/dt, the gate driver must be capable of providing the

QGD charge in 20 ns or less. In other words, a peak current of 1.65 A (= 33 nC / 20 ns) or higher must be

provided by the gate driver. The LM5134 gate driver is capable of providing 4.5-A peak sourcing current, which

exceeds the design requirement and has the capability to meet the switching speed needed. The 2.7x overdrive

capability provides an extra margin against part-to-part variations in the QGD parameter of the power MOSFET,

along with additional flexibility to insert external gate resistors and fine tune the switching speed for efficiency

versus EMI optimizations.

However, in practical designs the parasitic trace inductance in the gate drive circuit of the PCB will have a

definitive role to play on the power MOSFET switching speed. The effect of this trace inductance is to limit the

dI/dt of the output current pulse of the gate driver. To illustrate this, consider output current pulse waveform from

the gate driver to be approximated to a triangular profile, where the area under the triangle ( ½ × I PEAK × time)

would equal the total gate charge of the power MOSFET (QG parameter in SPP20N60C3 power MOSFET

datasheet = 87 nC typical). If the parasitic trace inductance limits the dI/dt, then a situation may occur in which

the full peak current capability of the gate driver is not fully achieved in the time required to deliver the QG

required for the power MOSFET switching. In other words, the time parameter in the equation would dominate

and the I PEAK value of the current pulse would be much less than the true peak current capability of the device,

while the required QG is still delivered. Because of this, the desired switching speed may not be realized, even

when theoretical calculations indicate the gate driver is capable of achieving the targeted switching speed. Thus,

placing the gate driver device very close to the power MOSFET and designing a tight gate drive-loop with

minimal PCB trace inductance is important to realize the full peak-current capability of the gate driver.

The LM5134 is capable of driving a small FET local to the Gate of the main MOSFET to reduce the impact of this

parasitic inductance and achieve the high dV/dt required on turnoff. The nominal gate voltage plateau of the

SPP20N60C3 is given as 5.5 V. Thus to achieve the required sink current of 1.65 A would require an Rds_on of

3.3

Ω for the pilot FET. Lower on resistance gives further margin in the turnoff speed as described above, and

reduces the potential for false turnon.

8.2.2.5

Enable and Disable Function

Certain applications demand independent control of the output state of the driver, without involving the input

signal. A pin offering an enable and disable function achieves this requirement. The LM5134 device offers two

input pins, IN+ and IN – , both of which control the state of the output as listed in Table 2. Based on whether an

inverting or noninverting input signal is provided to the driver, the appropriate input pin can be selected as the

primary input for controlling the gate driver. The other unused input pin can be used for the enable and disable

functionality. If the design does not require an enable function, the unused input pin can be tied to either the VDD

pin (in case IN+ is the unused pin), or GND (in case IN – is unused pin) to ensure it does not affect the output

status.