DP8420V datasheet(11/60 Pages) NSC

11 / 60 page

30 Programming and Resetting (Continued)

33 PROGRAMMING BIT DEFINITIONS

(Continued)

Symbol

Description

C6 C5 C4

RAS and CAS Configuration Modes

(Continued)

1 0 1

RAS and CAS pairs are selected by B1 ECASn must be asserted for CASn to be asserted

B1 e 0 during an access selects RAS0 – 1 and CAS0–1

B1 e 1 during an access selects RAS2 – 3 and CAS2–3

B0 is not used during an access

No error scrubbing

1 1 0

RAS singles are selected by B0 – 1 CAS0 – 3 are all selected ECASn must be asserted for CASntobe

asserted

B1 e 0 B0 e 0 during an access selects RAS0 and CAS0–3

B1 e 0 B0 e 1 during an access selects RAS1 and CAS0–3

B1 e 1 B0 e 0 during an access selects RAS2 and CAS0–3

B1 e 1 B0 e 1 during an access selects RAS3 and CAS0–3

No error scrubbing

1 1 1

RAS and CAS singles are selected by B0 1 ECASn must be asserted for CASn to be asserted

B1 e 0 B0 e 0 during an access selects RAS0 and CAS0

B1 e 0 B0 e 1 during an access selects RAS1 and CAS1

B1 e 1 B0 e 0 during an access selects RAS2 and CAS2

B1 e 1 B0 e 1 during an access selects RAS3 and CAS3

No error scrubbing

Refresh Clock Fine Tune Divisor

Divide delay linerefresh clock further by 30 (If DELCLKRefresh Clock Clock Divisor e 2 MHz e 15 ms

refresh period)

Divide delay linerefresh clock further by 26 (If DELCLKRefresh Clock Clock Divisor e 2 MHz e 13 ms

refresh period)

C2 C1 C0

Delay LineRefresh Clock Divisor Select

0 0 0

Divide DELCLK by 10 to get as close to 2 MHz as possible

0 0 1

Divide DELCLK by 9 to get as close to 2 MHz as possible

0 1 0

Divide DELCLK by 8 to get as close to 2 MHz as possible

0 1 1

Divide DELCLK by 7 to get as close to 2 MHz as possible

1 0 0

Divide DELCLK by 6 to get as close to 2 MHz as possible

1 0 1

Divide DELCLK by 5 to get as close to 2 MHz as possible

1 1 0

Divide DELCLK by 4 to get as close to 2 MHz as possible

1 1 1

Divide DELCLK by 3 to get as close to 2 MHz as possible

Refresh Mode Select

RAS0 – 3 will all assert and negate at the same time during a refresh

Staggered Refresh RAS outputs during refresh are separated by one positive clock edge Depending on the

configuration mode chosen either one or two RASs will be asserted

Address Pipelining Select

Address pipelining is selected The DRAM controller will switch the DRAM column address back to the row

address after guaranteeing the column address hold time

Non-address pipelining is selected The DRAM controller will hold the column address on the DRAM address

bus until the access RASs are negated

WAIT or DTACK Select

WAIT type output is selected

DTACK (Data Transfer ACKnowledge) type output is selected

Add Wait States to the Current Access if WAITIN is Low

WAIT or DTACK will be delayed by one additional positive edge of CLK

WAIT or DTACK will be delayed by two additional positive edges of CLK

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