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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP8420V датащи(PDF) 1 Page - National Semiconductor (TI) |
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DP8420V датащи(HTML) 1 Page - National Semiconductor (TI) |
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1 / 60 page  TLF11109 May 1992 DP8420V21V22V-33 DP84T22-25 microCMOS Programmable 256k1M4M Dynamic RAM ControllerDrivers General Description The DP8420V21V22V-33 DP84T22-25 dynamic RAM controllers provide a low cost single chip interface between dynamic RAM and all 8- 16- and 32-bit systems The DP8420V21V22V-33 DP84T22-25 generate all the re- quired access control signal timing for DRAMs An on-chip refresh request clock is used to automatically refresh the DRAM array Refreshes and accesses are arbitrated on chip If necessary a WAIT or DTACK output inserts wait states into system access cycles including burst mode ac- cesses RAS low time during refreshes and RAS precharge time after refreshes and back to back accesses are guaran- teed through the insertion of wait states Separate on-chip precharge counters for each RAS output can be used for memory interleaving to avoid delayed back to back access- es because of precharge An additional feature of the DP8422V DP84T22 is two access ports to simplify dual ac- cessing Arbitration among these ports and refresh is done on chip To make board level circuit testing easier the DP84T22 incorporates TRI-STATE output buffers Features Y On chip high precision delay line to guarantee critical DRAM access timing parameters Y microCMOS process for low power Y High capacitance drivers for RAS CAS WE and DRAM address on chip Y On chip support for nibble page and static column DRAMs Y TRI-STATE outputs (DP84T22 only) Y Byte enable signals on chip allow byte writing in a word size up to 32 bits with no external logic Y Selection of controller speeds 25 MHz and 33 MHz Y On board Port APort B (DP8422V DP84T22 only)re- fresh arbitration logic Y Direct interface to all major microprocessors (applica- tion notes available) Y 4 RAS and 4 CAS drivers (the RAS and CAS configura- tion is programmable) of Pins of Address Largest Direct Drive Access Control (PLCC) Outputs DRAM Memory Ports Possible Capacity Available DP8420V 68 9 256 kbit 4 Mbytes Single Access Port DP8421V 68 10 1 Mbit 16 Mbytes Single Access Port DP8422V 84 11 4 Mbit 64 Mbytes Dual Access Ports (A and B) DP84T22 84 11 4 Mbit 64 Mbytes Dual Access and TRI-STATE Block Diagram DP8420V21V22V DP74T22 DRAM Controller TLF11109 – 1 FIGURE 1 TRI-STATE is a registered trademark of National Semiconductor Corporation Staggered RefreshTM is a trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
Аналогичный номер детали - DP8420V |
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Аналогичное описание - DP8420V |
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ссылки URL |
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