DP8420V datasheet(8/60 Pages) NSC

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30 Programming and Resetting

Due to the variety in power supplies power-up times an

EXTERNAL RESET must be performed before the DRAM

controller can be programmed and used

After going through the reset procedure the DP8420V

21V22V DP84T22 can be programmed by either of two

methods Mode Load Only Programming or Chip Select Ac-

cess Programming After programming the DRC for the first

time after reset the chip enters a 60 ms initialization period

during this period the controller performs refreshes every

13 msor15 ms this makes further DRAM warm up cycles

unnecessary

After this stage the chip can be repro-

grammed as many times as the user wishes and the 60 ms

period will not be entered into unless the chip is reset and

programmed again

During the 60 ms initialization period RFIP is asserted low

and RAS toggles every 13 msor15 ms depending on the

programming bit for refresh (C3) CAS will be inactive (logic

1) and the ‘‘Q’’ outputs will count from 0 to 2047 refreshing

the entire DRAM array The actual initialization time period

is given by the following formula T e 4096 (Clock Divisor

Select) (Refresh Clock Fine Tune)(DELCLK Frq)

31 EXTERNAL RESET

At power up if the internal power up reset worked all inter-

nal latches and flip-flops are cleared and the part is ready to

be programmed The power up state can also be achieved

by performing an External Reset which is required to insure

proper operation External Reset is achieved by asserting

ML and DISRFSH for at least 16 positive clock edges In

order to perform simply a Reset the ML signal must be

negated before DISRFSH is negated as shown in

Figure 5a

This procedure will only reset the controller which now is

ready for programming

While performing an External Reset if the user negates

DISRFSH at least one clock period before negating ML as

shown in

Figure 5b ML negated will program the DP8420V

21V22V DP84T22 with the values in R0 – 9 C0 – 9 B0 – 1

and ECAS0 The 60 ms initialization period will be entered

since it is the first programming after reset This is a good

way of resetting and programming the part at the same time

Make sure the right programming bits are on the address

bus before ML is negated

The DRC may be programmed any time on the fly but the

user must make sure that No Access or Refresh is in prog-

ress Reset is asynchronous

TLF11109 – 5

FIGURE 5a Chip Reset but Not Programmed

TLF11109 – 6

FIGURE 5b Chip Reset and Programmed

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