Jitter Characteristics in Input Clock Mode

f − Single-Sideband Frequency − Hz

G001

−160

−140

−120

−100

−80

−60

−40

−20

0

10

100

1k

100M

10k

100k

1M

10M

CDCE421

If the CDCE421 is being referenced by an external and cleaner LVCMOS input of 35.42 MHz, Figure 6 shows

the SSB phase noise plot of the output at 708 MHz from 100 Hz to 40 MHz from the carrier. Note the

dependence of output jitter on the input reference jitter. See Figure 11 for test setup.

Figure 6. Phase Noise Plot for LVPECL Output at 708 MHz

Table 3. Phase Noise Parameters With LVCMOS Input of 35.4 MHz and LVPECL Output at 708 MHz

Phase noise specifications under following assumptions: input frequency f = 35.42 MHz (VCO = 2, prescaler = 3, output divider =

PARAMETER

MIN

TYP

MAX

UNIT

Phase noise at 100 Hz

–95

dBc/Hz

Phase noise at 1 kHz

–105

dBc/Hz

Phase noise at 10 kHz

–109

dBc/Hz

Phase noise at 100 kHz

–114

dBc/Hz

Phase noise at 1 MHz

–126

dBc/Hz

Phase noise at 10 MHz

–146

dBc/Hz

Phase noise at 20 MHz

–146

dBc/Hz

RMS jitter integrated from 12 kHz to 20 MHz

438

fs

14

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