DEVICE SETUP EXAMPLE

f

OutputDivider

FeedbackDivider

f

1

20

622.08 + 31.154 MHz

(2)

SERIAL INTERFACE AND CONTROL

CDCE421

The following example illustrates the procedure to calculate the required AT-cut crystal frequency needed to

generate a desired output frequency.

Assuming the requirement to generate an output frequency of 622.08 MHz, Table 1 shows that the desired

output frequency lies between 583.5 MHz and 680 MHz.

REQUIRED INPUT

DESIRED OUTPUT

CRYSTAL

VCO

OUTPUT

PRESCALER

FEEDBACK

FREQUENCY (MHz)

FREQUENCY (MHz)

SELECTION

DIVIDER

SETTING

From

To

From

To

650.0

766.7

32.500

38.333

VCO 2

1

3

20

583.5

650.0

29.174

32.500

VCO 1

1

3

20

510.0

587.5

31.875

36.719

VCO 2

1

4

16

(1)

The feedback divider is set automatically with respect to the prescaler setting.

So this means that the device must be configured with:

VCO = VCO 1

Output divider = 1

Prescaler setting = 3

To determine the correct crystal frequency needed to get 622.08 MHz with these settings, substitute values into

Equation 1.

The AT-cut frequency should be 31.154 MHz (between 29.174 MHz and 32.500 MHz, as shown in Table 1) .

The CDCE421 uses a unique Texas Instruments proprietary interface protocol that can be configured and

programmed via a single input pin to the device. The architecture enables only writing to the device from this

input pin. Reading the content of a register can be achieved by sending a read command on the input pin and

monitoring the output pins (LVDS or LVPECL). In cases where the output pins cannot be used to read the

content, the software controlling the interface must account for what is written to the EEPROM and when it is

programmed. Monitoring the outputs verifies the programming modes, and cycling power on the device verifies

that the EEPROM is holding the proper configuration.

The CDCE421 can be configured and programmed via the SDATA input pin. For this purpose, a square-wave

programming sequence must be written to the device as described in the following section. During the EEPROM

After each Write to WordX, the written data are latched, made effective, and offer look-ahead before the actual

data are stored into the EEPROM.

The following table summarizes all valid programming commands.

SDATA

FUNCTION

00 1100

Enter Programming Mode (State 1

→ State 2); bits must be sent in the specified order with the specified timing.

Otherwise, a time-out occurs.

11 1011

Enter Register Read Back Mode; bits must be sent in the specified order with the specified timing. Otherwise, a

time-out occurs.

000 xxxx xxxx

100 xxxx xxxx

010 xxxx xxxx

110 xxxx xxxx

(1)

Each rising edge causes a bit to be latched.

(2)

Between the bits, some longer time delays can occur, but this has no effect on the data.

(3)

A Write to WordX is expected to be 10 bits long. After the 10th bit, the respective word is latched and its effect can be observed as

look-ahead function.

4

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