PACKAGE (QFN24)

NC

VCC

15

14

13

RGEPACKAGE

(TOP VIEW)

CDCE421

NC

1

2

3

SDATA

4

NC

5

NC

18

NC

17

VCC

16

NC

NC

CE

NC

P0024-05

6

PIN DESCRIPTIONS

CDCE421

The CDCE421 is available in a QFN 24-pin package. The QFN package footprint is illustrated in Figure 5, as well

as the pad locations and numbers.

Figure 5. Pinout of the CDCE421 QFN-24 Package

Table 2 shows the pin descriptions for the CDCE421 QFN-24 package.

Table 2. CDCE421 Pin Descriptions

TERMINAL

TERMINAL

ESD

TYPE

DESCRIPTION

NAME

NO.

PROTECTION

Chip enable

CE = 1: enable the device and the outputs.

CE

1

I

Y

CE = 0: disable all current sources; in LVDS mode, LVDSP = LVDSN = Hi-Z;

in LVPECL mode, LVPECLP = LVPECLN = Hi-Z.

GND

8, 9

GND

Y

Ground

2, 4–6,

No connect

11–15,

Do not connect these pins. Leave them floating.

18–20, 23,24

High-speed negative differential LVPECL or LVDS outputs. (Outputs are

OUTN

7

O

Y

enabled by CE and selected by the EEPROM configuration registers.)

High-speed positive differential LVPECL or LVDS outputs. (Outputs are

OUTP

10

O

Y

enabled by CE and selected by the EEPROM configuration registers.)

SDATA

3

I

Y

Programming pin using TI proprietary interface protocol

VCC

16, 17

Power

Y

3.3-V power supply

In crystal input mode, connect XIN1 to one end of the crystal and XIN2 to the

XIN 1

21

I

Y

other end of the crystal. In LVCMOS input single-ended driven mode, XIN1

XIN 2

22

GND/NC

N

(pin 21) acts as an input reference, and XIN2 should connect to GND or it can

be left unconnected.

Copyright © 2007–2009, Texas Instruments Incorporated

Submit Documentation Feedback

11

Product Folder Link(s): CDCE421