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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83256 датащи(PDF) 67 Page - Texas Instruments |
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DP83256 датащи(HTML) 67 Page - Texas Instruments |
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67 / 146 page  50 Registers (Continued) 522 LINK ERROR THRESHOLD REGISTER (LETR) The Link Error Threshold Register contains the start value for the Link Error Monitor Counter It is an 8-bit down-counter which decrements if link errors are detected When the Counter reaches 0 the Link Error Monitor Threshold Register value is loaded into the Link Error Monitor Counter and the Link Error Monitor Threshold bit (LEMT) of the Interrupt Condition Register (ICR) is set to one The Link Error Monitor Threshold Register value is also loaded into the Link Error Monitor Counter during every Control Bus Interface write cycle of LETR The counter is initialized to 0 during the reset process (ie ERSTeGND) ACCESS RULES ADDRESS READ WRITE 15h Always Always D7 D6 D5 D4 D3 D2 D1 D0 LET7 LET6 LET5 LET4 LET3 LET2 LET1 LET0 Bit Symbol Description D0 – D7 LET0 – LET7 LINK ERROR THRESHOLD BIT k0–7l Start value for the Link Error Monitor Counter LET0 is the Least Significant Bit (LSB) 66 |
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