DP83256 datasheet(56/146 Pages) TI1

56 / 146 page

50 Registers (Continued)

511 RECEIVE CONDITION REGISTER B (RCRB)

The Receive Condition Register B maintains a historical record of the Lines States recognized by the Receiver Block

When a new Line State is entered the bit corresponding to that line state is set to 1 The bits corresponding to the previous Line

States are not cleared thereby maintaining a record of the Line States detected

The Receive Condition B bit (RCB) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the

Receive Condition Register B is set to 1 and the corresponding mask bit(s) in Receive Condition Mask Register B (RCMRB) is

also set to 1

ACCESS RULES

ADDRESS

READ

WRITE

0Ah

Always

Conditional

RES

SILS

EBOU

CSE

LSUPV

ALS

ILS

Bit

Symbol

Description

ILS

IDLE LINE STATE

Received a minimum of two consecutive Idle symbol pairs (11111 11111)

STATE THRESHOLD

This bit will be set to 1 when the internal State Counter reaches zero It will remain set until

a value equal to or greater than one is loaded into the State Threshold Register or State Prescale Threshold

During the reset process (ie ERSTeGND) since the State Counter is initialized to 0 the State Threshold bit is

set to 1

ALS

ACTIVE LINE STATE

Received a JK symbol pair (11000 10001) and possibly data symbols following

LSUPV

LINE STATE UNKNOWN AND PHY VALID

The Receiver Block has not detected the minimum conditions to

enter a known line state

In addition the most recently known line state was either Active Line State or Idle Line State

CSE

CONNECTION SERVICE EVENTCASCADE SYNCHRONIZATION ERROR

When one or more bits in the CMT Condition Register (CMTCR) are set and the corresponding bit(s) in the CMT

Condition Mask Register (CMTCMR) are set the Connection service event bit will be set to a 1

When a synchronization error occurs the Cascade Synchronization Error bit is set to 1 A synchronization error

occurs if the Cascade Start signal (CS) is not asserted within approximately 80 ns of Cascade Ready (CR) release

Note

Cascade mode and the CMT features can not be used at the same time

Note

Cascade mode is only supported on the DP83257 device

EBOU

ELASTICITY BUFFER UNDERFLOW

OVERFLOW

The Elasticity Buffer has either overflowed or underflowed

The Elasticity Buffer will automatically recover if the condition which caused the error is only transient but the

event bit will remain set until cleared by software

SILS

SUPER IDLE LINE STATE

Received a minimum of eight Idle symbol pairs (11111 11111)

RES

RESERVED

Reserved for future use

Note

Users are discouraged from using these bits The reserved bits are reset to 0 during the reset process They may be set or cleared without

any effects to the functionality of the PLAYERa device

DP83256 датащи(PDF) 56 Page - Texas Instruments

DP83256 датащи(HTML) 56 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL