DP83256 datasheet(48/146 Pages) TI1

48 / 146 page

50 Registers (Continued)

54 INTERRUPT CONDITION MASK REGISTER (ICMR)

The Interrupt Condition Mask Register allows the user to dynamically select which events will generate an interrupt

The Interrupt pin will be asserted (ie EINT e GND) when one or more bits within the Interrupt Condition Register (ICR) are set

to 1 and the corresponding mask bits in this register are also set to 1

This register is cleared (ie set to 0) and all interrupts are initially masked during the reset process

ACCESS RULES

ADDRESS

READ

WRITE

03h

Always

UDIM

RCBM

RCAM

LEMTM

CWIM

CCRM

CPEM

DPEM

Bit

Symbol

Description

DPEM

PHY

REQUEST

DATA PARITY ERROR MASK

The mask bit for the PHY

Request Data Parity Error bit

(DPE) of the Interrupt Condition Register (ICR)

CPEM

Control Bus DATA PARITY ERROR MASK

The mask bit for the Control Bus Data Parity Error bit (CPE) of the

Interrupt Condition Register (ICR)

CCRM

Control Bus WRITE COMMAND REJECT MASK

The mask bit for the Control Bus Write Command Reject bit

(CCR) of the Interrupt Condition Register (ICR)

CWIM

CONDITIONAL WRITE INHIBIT MASK

The mask bit for the Conditional Write Inhibit bit (CWI) of the Interrupt

Condition Register (ICR)

LEMTM

LINK ERROR MONITOR THRESHOLD MASK

The mask bit for the Link Error Monitor Threshold bit (LEMT) of

the Interrupt Condition Register (ICR)

RCAM

RECEIVE CONDITION A MASK

The mask bit for the Receive Condition A bit (RCA) of the Interrupt Condition

RCBM

RECEIVE CONDITION B MASK

The mask bit for the Receive Condition B bit (RCB) of the Interrupt Condition

UDIM

USER DEFINABLE INTERRUPT MASK

The mask bit for the User Definable Interrupt bit (UDI) of the Interrupt

Condition Register (ICR)

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