DP83847 datasheet(22/60 Pages) NSC

22 / 60 page

www.national.com

period of 120

µs. Left uncompensated, events such as this

can cause packet loss.

3.3.2 Signal Detect

The signal detect function of the DP83847 is incorporated

to meet the specifications mandated by the ANSI FDDI TP-

PMD Standard as well as the IEEE 802.3 100BASE-TX

Standard for both voltage thresholds and timing parame-

ters.

Note that the reception of normal 10BASE-T link pulses

and fast link pulses per IEEE 802.3u Auto-Negotiation by

the 100BASE-TX receiver do not cause the DP83847 to

assert signal detect.

3.3.3 Digital Adaptive Equalization

When transmitting data at high speeds over copper twisted

pair cable, frequency dependent attenuation becomes a

concern. In high-speed twisted pair signalling, the fre-

quency content of the transmitted signal can vary greatly

during normal operation based primarily on the random-

ness of the scrambled data stream. This variation in signal

attenuation caused by frequency variations must be com-

pensated for to ensure the integrity of the transmission.

In order to ensure quality transmission when employing

MLT-3 encoding, the compensation must be able to adapt

to various cable lengths and cable types depending on the

installed environment. The selection of long cable lengths

for a given implementation, requires significant compensa-

tion which will over-compensate for shorter, less attenuat-

ing

lengths.

Conversely,

the

selection

short

intermediate cable lengths requiring less compensation will

cause serious under-compensation for longer length

cables. The compensation or equalization must be adap-

tive to ensure proper conditioning of the received signal

independent of the cable length.

The DP83847 utilizes a extremely robust equalization

scheme referred as ‘Digital Adaptive Equalization’. Tradi-

tional designs use a pseudo adaptive equalization scheme

that determines the approximate cable length by monitor-

ing signal attenuation at certain frequencies. This attenua-

tion value was compared to the internal receive input

reference voltage. This comparison would indicate the

amount of equalization to use. Although this scheme is

used successfully on the DP83223V twister, it is sensitive

to transformer mismatch, resistor variation and process

induced offset. The DP83223V also required an external

attenuation network to help match the incoming signal

amplitude to the internal reference.

The Digital Equalizer removes ISI (inter symbol interfer-

ence) from the receive data stream by continuously adapt-

ing to provide a filter with the inverse frequency response

of the channel. When used in conjunction with a gain

stage, this enables the receive 'eye pattern' to be opened

sufficiently to allow very reliable data recovery.

Traditionally 'adaptive' equalizers selected 1 of N filters in

an attempt to match the cables characteristics. This

approach will typically leave holes at certain cable lengths,

where the performance of the equalizer is not optimized.

The DP83847 equalizer is truly adaptive to any length of

cable up to 150m.

3.3.4 Clock Recovery Module

The Clock Recovery Module (CRM) accepts 125 Mb/s

MLT3 data from the equalizer. The DPLL locks onto the

125 Mb/s data stream and extracts a 125 MHz recovered

clock. The extracted and synchronized clock and data are

used as required by the synchronous receive operations as

generally depicted in Figure 7.

The CRM is implemented using an advanced all digital

Phase Locked Loop (PLL) architecture that replaces sensi-

tive analog circuitry. Using digital PLL circuitry allows the

DP83847 to be manufactured and specified to tighter toler-

ances.

3.3.5 NRZI to NRZ

In a typical application, the NRZI to NRZ decoder is

required in order to present NRZ formatted data to the

descrambler (or to the code-group alignment block, if the

descrambler is bypassed, or directly to the PCS, if the

receiver is bypassed).

3.3.6 Serial to Parallel

The 100BASE-TX receiver includes a Serial to Parallel

converter which supplies 5-bit wide data symbols to the

PCS Rx state machine.

3.3.7 Descrambler

A serial descrambler is used to de-scramble the received

NRZ data. The descrambler has to generate an identical

data scrambling sequence (N) in order to recover the origi-

nal unscrambled data (UD) from the scrambled data (SD)

as represented in the equations:

Synchronization of the descrambler to the original scram-

bling sequence (N) is achieved based on the knowledge

that the incoming scrambled data stream consists of

scrambled IDLE data. After the descrambler has recog-

nized 12 consecutive IDLE code-groups, where an

unscrambled IDLE code-group in 5B NRZ is equal to five

consecutive ones (11111), it will synchronize to the receive

data stream and generate unscrambled data in the form of

unaligned 5B code-groups.

In order to maintain synchronization, the descrambler must

continuously monitor the validity of the unscrambled data

that it generates. To ensure this, a line state monitor and a

hold timer are used to constantly monitor the synchroniza-

tion status. Upon synchronization of the descrambler the

hold timer starts a 722

µs countdown. Upon detection of

sufficient IDLE code-groups (58 bit times) within the 722

µs

period, the hold timer will reset and begin a new count-

down. This monitoring operation will continue indefinitely

given a properly operating network connection with good

signal integrity. If the line state monitor does not recognize

sufficient unscrambled IDLE code-groups within the 722

µs

period, the entire descrambler will be forced out of the cur-

rent state of synchronization and reset in order to re-

acquire synchronization.

3.3.8 Code-group Alignment

The code-group alignment module operates on unaligned

5-bit data from the descrambler (or, if the descrambler is

bypassed, directly from the NRZI/NRZ decoder) and con-

verts it into 5B code-group data (5 bits). Code-group align-

ment occurs after the J/K code-group pair is detected.

Once the J/K code-group pair (11000 10001) is detected,

subsequent data is aligned on a fixed boundary.

⊕

()

⊕

()

DP83847 датащи(PDF) 22 Page - National Semiconductor (TI)

DP83847 датащи(HTML) 22 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

датащи скачать

ссылки URL