DP83847 datasheet(16/60 Pages) NSC

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returning a one in this bit, then the station management

entity need not generate preamble for each management

transaction.

The DP83847 requires a single initialization sequence of

32 bits of preamble following hardware/software reset. This

requirement is generally met by the mandatory pull-up

resistor on MDIO in conjunction with a continuous MDC, or

the management access made to determine whether Pre-

amble Suppression is supported.

While the DP83847 requires an initial preamble sequence

of 32 bits for management initialization, it does not require

a full 32-bit sequence between each subsequent transac-

tion. A minimum of one idle bit between management

transactions is required as specified in IEEE 802.3u.

3.1.4 PHY Address Sensing

The DP83847 provides five PHY address pins, the informa-

tion is latched into the PHYCTRL register (address 19h,

bits [4:0]) at device power-up/Hardware reset.

The DP83847 supports PHY Address strapping values 0

(<00000>) through 31 (<11111>). Strapping PHY Address

0 puts the part into Isolate Mode. It should also be noted

that selecting PHY Address 0 via an MDIO write to PHYC-

TRL will not put the device in Isolate Mode; Address 0 must

be strapped in.

3.1.5 Nibble-wide MII Data Interface

Clause 22 of the IEEE 802.3u specification defines the

Media Independent Interface. This interface includes a

dedicated receive bus and a dedicated transmit bus. These

two data buses, along with various control and indicate sig-

nals, allow for the simultaneous exchange of data between

the DP83847 and the upper layer agent (MAC).

The receive interface consists of a nibble wide data bus

RXD[3:0], a receive error signal RX_ER, a receive data

valid flag RX_DV, and a receive clock RX_CLK for syn-

chronous transfer of the data. The receive clock can oper-

ate at either 2.5 MHz to support 10 Mb/s operation modes

or at 25 MHz to support 100 Mb/s operational modes.

The transmit interface consists of a nibble wide data bus

TXD[3:0], a transmit enable control signal TX_EN, and a

transmit clock TX_CLK which runs at either 2.5 MHz or 25

MHz.

Additionally, the MII includes the carrier sense signal CRS,

as well as a collision detect signal COL. The CRS signal

asserts to indicate the reception of data from the network

or as a function of transmit data in Half Duplex mode. The

COL signal asserts as an indication of a collision which can

occur during half-duplex operation when both a transmit

and receive operation occur simultaneously.

3.1.6 Collision Detect

For Half Duplex, a 10BASE-T or 100BASE-TX collision is

detected when the receive and transmit channels are

active simultaneously. Collisions are reported by the COL

signal on the MII.

If the DP83847 is transmitting in 10 Mb/s mode when a col-

lision is detected, the collision is not reported until seven

bits have been received while in the collision state. This

prevents a collision being reported incorrectly due to noise

on the network. The COL signal remains set for the dura-

tion of the collision.

If a collision occurs during a receive operation, it is immedi-

ately reported by the COL signal.

When heartbeat is enabled (only applicable to 10 Mb/s

operation), approximately 1

µs after the transmission of

each packet, a Signal Quality Error (SQE) signal of approx-

imately 10 bit times is generated (internally) to indicate

successful transmission. SQE is reported as a pulse on the

COL signal of the MII.

3.1.7 Carrier Sense

Carrier Sense (CRS) may be asserted due to receive activ-

ity, once valid data is detected via the squelch function dur-

ing 10 Mb/s operation. During 100 Mb/s operation CRS is

asserted when a valid link (SD) and two non-contiguous

zeros are detected on the line.

For 10 or 100 Mb/s Half Duplex operation, CRS is asserted

during either packet transmission or reception.

For 10 or 100 Mb/s Full Duplex operation, CRS is asserted

only due to receive activity.

CRS is deasserted following an end of packet.

3.2 100BASE-TX TRANSMITTER

The 100BASE-TX transmitter consists of several functional

blocks which convert synchronous 4-bit nibble data, as pro-

vided by the MII, to a scrambled MLT-3 125 Mb/s serial

data stream. Because the 100BASE-TX TP-PMD is inte-

grated, the differential output pins, TD

±, can be directly

routed to the magnetics.

The block diagram in Figure 5 provides an overview of

each functional block within the 100BASE-TX transmit sec-

tion.

The Transmitter section consists of the following functional

blocks:

— Code-group Encoder and Injection block (bypass option)

— Scrambler block (bypass option)

— NRZ to NRZI encoder block

— Binary to MLT-3 converter / Common Driver

Figure 3. Typical MDC/MDIO Write Operation

MDC

MDIO

11 0 0 0 0 000

(STA)

Idle

Start

Opcode

(Write)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR)

0 0 0

0 00

0 0 0 0 0 000 Z

Idle

10 0

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