DP83847 datasheet(12/60 Pages) NSC

12 / 60 page

www.national.com

The BMSR also provides status on:

— Whether Auto-Negotiation is complete

— Whether the Link Partner is advertising that a remote

fault has occurred

— Whether valid link has been established

— Support for Management Frame Preamble suppression

The Auto-Negotiation Advertisement Register (ANAR) indi-

cates the Auto-Negotiation abilities to be advertised by the

DP83847. All available abilities are transmitted by default,

but any ability can be suppressed by writing to the ANAR.

Updating the ANAR to suppress an ability is one way for a

management agent to change (force) the technology that is

used.

The

Auto-Negotiation

Link

Partner

Ability

(ANLPAR) at address 05h is used to receive the base link

code word as well as all next page code words during the

negotiation. Furthermore, the ANLPAR will be updated to

either 0081h or 0021h for parallel detection to either 100

Mb/s or 10 Mb/s respectively.

The Auto-Negotiation Expansion Register (ANER) indi-

cates additional Auto-Negotiation status. The ANER pro-

vides status on:

— Whether a Parallel Detect Fault has occurred

— Whether the Link Partner supports the Next Page func-

tion

— Whether the DP83847 supports the Next Page function

— Whether the current page being exchanged by Auto-Ne-

gotiation has been received

— Whether the Link Partner supports Auto-Negotiation

2.1.3 Auto-Negotiation Parallel Detection

The DP83847 supports the Parallel Detection function as

defined in the IEEE 802.3u specification. Parallel Detection

requires both the 10 Mb/s and 100 Mb/s receivers to moni-

tor the receive signal and report link status to the Auto-

Negotiation function. Auto-Negotiation uses this informa-

tion to configure the correct technology in the event that the

Link Partner does not support Auto-Negotiation but is

transmitting link signals that the 100BASE-TX or 10BASE-

T PMAs recognize as valid link signals.

If the DP83847 completes Auto-Negotiation as a result of

Parallel Detection, bits 5 and 7 within the ANLPAR register

will be set to reflect the mode of operation present in the

Link Partner. Note that bits 4:0 of the ANLPAR will also be

set to 00001 based on a successful parallel detection to

indicate a valid 802.3 selector field. Software may deter-

mine that negotiation completed via Parallel Detection by

reading a zero in the Link Partner Auto-Negotiation Able

bit, once the Auto-Negotiation Complete bit is set. If config-

ured for parallel detect mode and any condition other than

a single good link occurs then the parallel detect fault bit

will set.

2.1.4 Auto-Negotiation Restart

Once Auto-Negotiation has completed, it may be restarted

at any time by setting bit 9 (Restart Auto-Negotiation) of the

BMCR to one. If the mode configured by a successful Auto-

Negotiation loses a valid link, then the Auto-Negotiation

process will resume and attempt to determine the configu-

ration for the link. This function ensures that a valid config-

uration is maintained if the cable becomes disconnected.

A renegotiation request from any entity, such as a manage-

ment agent, will cause the DP83847 to halt any transmit

data and link pulse activity until the break_link_timer

expires (~1500 ms). Consequently, the Link Partner will go

into link fail and normal Auto-Negotiation resumes. The

DP83847

will

resume

Auto-Negotiation

after

the

break_link_timer has expired by issuing FLP (Fast Link

Pulse) bursts.

2.1.5 Enabling Auto-Negotiation via Software

It is important to note that if the DP83847 has been initial-

ized upon power-up as a non-auto-negotiating device

(forced technology), and it is then required that Auto-Nego-

tiation or re-Auto-Negotiation be initiated via software,

bit 12 (Auto-Negotiation Enable) of the Basic Mode Control

Negotiation function to take effect.

2.1.6 Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation take approximately

2-3 seconds to complete. In addition, Auto-Negotiation with

next page should take approximately 2-3 seconds to com-

plete, depending on the number of next pages sent.

Refer to Clause 28 of the IEEE 802.3u standard for a full

description of the individual timers related to Auto-Negotia-

tion.

2.2 PHY Address and LEDs

The 5 PHY address inputs pins are shared with the LED

pins as shown below.

The DP83847 can be set to respond to any of 32 possible

PHY addresses. Each DP83847 or port sharing an MDIO

bus in a system must have a unique physical address.

Refer to Section 3.1.4, PHY Address Sensing section for

more details.

The state of each of the PHYAD inputs latched into the

PHYCTRL register bits [4:0]at system power-up/reset

depends on whether a pull-up or pull-down resistor has

been installed for each pin. For further detail relating to the

latch-in timing requirements of the PHY Address pins, as

well as the other hardware configuration pins, refer to the

Reset summary in Section 4.0.

Since the PHYAD strap options share the LED output pins,

the external components required for strapping and LED

usage must be considered in order to avoid contention.

Specifically, when the LED outputs are used to drive LEDs

directly, the active state of each output driver is dependent

on the logic level sampled by the corresponding PHYAD

input upon power-up/reset. For example, if a given PHYAD

input is resistively pulled low then the corresponding output

will be configured as an active high driver. Conversely, if a

Table 2. PHY Address Mapping

Pin #

PHYAD Function

LED Function

PHYAD0

Duplex

PHYAD1

COL

PHYAD2

Good Link

PHYAD3

TX Activity

PHYAD4

RX Activity

n/a

Speed

DP83847 датащи(PDF) 12 Page - National Semiconductor (TI)

DP83847 датащи(HTML) 12 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

датащи скачать

ссылки URL