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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83266 датащи(PDF) 69 Page - National Semiconductor (TI) |
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DP83266 датащи(HTML) 69 Page - National Semiconductor (TI) |
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69 / 152 page  70 Control Information (Continued) Counter Overflow Mask Register (COMR) The Counter Overflow Mask Register (COMR) is used to mask bits from the Counter Overflow Latch Register (COLR) If a bit in Register COMR is set to One the corresponding bit in Register COLR will be applied to the Interrupt Condition Register which can then be used to generate an interrupt to the CPU All bits in this register are set to Zero upon reset Access Rules Address Read Write 01Dh Always Always Register Bits D7 D6 D5 D4 D3 D2 D1 D0 RES TKRCVD FRTRX FRNCOP FRCOP FRLST FREI FRRCV Bit Symbol Description D7 RES Reserved D6 TKRCVD Token Received Counter Overflow Mask This bit is used to mask COLRTKRCVD D5 FRTRX Frame Transmitted Counter Overflow Mask This bit is used to mask COLRFRTRX D4 FRNCOP Frame Not Copied Counter Overflow Mask This bit is used to mask COLRFRNCOP D3 FRCOP Frame Copied Counter Overflow Mask This bit is used to mask COLRFRCOP D2 FRLST Lost Frame Counter Overflow Mask This bit is used to mask COLRFRLST D1 FREI Error Isolated Counter Overflow Mask This bit is used to mask COLRFREI D0 FRRCV Frame Received Counter Overflow Mask This bit is used to mask COLRFRRCV 69 |
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