DP83266 datasheet(5/152 Pages) NSC

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20 General Features (Continued)

These paths allow error isolation at the device level

The MACSI device also supports through parity Even when

parity is not used by the system parity support can be pro-

vided across the PHY Interface

211 32-BIT ADDRESSDATA PATH TO HOST MEMORY

The MACSI device provides a 32-bit wide synchronous data

interface which permits connection to a standard multi-

master system bus operating from 125 MHz to 33 MHz or

to local memory using Big or Little Endian byte ordering

Demultiplexed addresses are provided on dedicated pins

Address information is also multiplexed on the data pins to

provide backward compatibility for designs based on the

BSI device The local memory may be static or dynamic For

maximum performance the MACSI device uses burst mode

transfers with four or eight 32-bit words to a burst To assist

the user with the burst transfer capability the three bits of

the address which cycle during a burst are output as demul-

tiplexed signals Maximum burst speed is one 32-bit word

per clock but slower speeds may be accommodated by in-

serting wait states

The MACSI device can operate within any combination of

cached non-cached paged or non-paged memory environ-

ments To provide this capability all data structures are con-

tained within a page boundary and bus transactions never

cross page boundaries The MACSI device performs all bus

transactions within aligned blocks to ease the interface to a

cached environment

212 MULTI-CHANNEL ARCHITECTURE

The MACSI device provides three Input Channels and two

Output Channels which are designed to operate indepen-

dently and concurrently They are separately configured by

the user to manage the reception or transmission of a par-

ticular kind of frame (for example synchronous frames

only)

213 SUPPORT FOR HEADERINFO SPLITTING

In order to support high performance protocol processing

the MACSI device can be programmed to split the header

and information portions of (non-MACSMT) frames be-

tween two Indicate Channels Frame bytes from the Frame

Control field (FC) up to the user-defined header length are

copied onto Indicate Channel 1 and the remaining bytes

(Info) are copied onto Indicate Channel 2 This is useful for

separating protocol headers from data and allows them to

be stored in different regions of memory to prevent unnec-

essary copying In addition a protocol monitor application

may decide to copy only the header portion of each frame

214 MAC BRIDGING SUPPORT

Support for bridging and monitoring applications is provided

by the InternalExternal Sorting Mode All frames matching

the external address (frames requiring bridging) are sorted

onto Indicate Channel 2 MAC and SMT frames matching

the internal (Ring Engine) address are sorted onto Indicate

Channel 0 and all other frames matching the device’s inter-

nal address (short or long) are sorted onto Indicate

Channel 1

215 ADDRESS BIT SWAPPING

The MACSI contains the necessary logic for swapping the

address fields within each frame between FDDI and IEEE

Canonical bit order This involves a bit reversal within each

byte of the address field (eg 08-00-17-C2-A1-03 would be-

come 1000E84385C0) This option is selectable on a per

channel basis and is supported on all transmit and receive

channels This is useful for bridging FDDI to Ethernet or for

swapping addresses for higher level protocols

216 STATUS BATCHING SERVICES

The MACSI device provides status for transmitted and re-

ceived frames Interrupts to the host are generated only at

status breakpoints which are defined by the user on a per

DMA Channel basis Breakpoints are selected when the

Channel is configured for operation To allow batching the

MACSI provides a status option called Tend that causes

the device to generate a single Confirmation Message De-

scriptor (CNF) for one or more Request Descriptors (REQs)

The MACSI device further reduces host processing time by

separating received frame status from the received data

This allows the CPU to scan quickly for errors when decid-

ing whether further processing should be done on received

frames If status was embedded in the data stream all data

would need to be read contiguously to find the Status Indi-

cator

217 RECEIVE FRAME FILTERING SERVICES

To increase performance and reliability the MACSI device

can be programmed to filter out identical MAC (same FC

and Info field) or SMT frames received from the ring Void

frames are filtered out automatically Filtering unnecessary

frames reduces the fill rate of the Indicate FIFO reduces

CPU frame processing time and reduces memory bus

transactions

218 TWO TIMING DOMAINS

To provide maximum performance and system flexibility the

MACSI device uses two independent clocks one for the

MAC (ring) Interface and one for the systemmemory bus

The MACSI device provides a fully synchronized interface

between these two timing domains

219 CLUSTERED INTERRUPTS

The MACSI device can be operated in a polled or interrupt-

driven environment The MACSI device provides the ability

to generate attentions (interrupts) at group boundaries

Some boundaries are pre-defined in hardware others are

defined by the user when the Channel is configured This

interrupt scheme significantly reduces the number of inter-

rupts to the host thus reducing host processing overhead

220 FIFO MEMORY

The MACSI device contains over 9 kBytes of on-chip FIFO

memory This memory includes separate 46 kByte FIFOs

for both the Transmit (Request) and Receive (Indicate) data

paths These data FIFOs allow the MACSI device to support

over 370 ms of bus latency for both transmit and receive

They also allow the MACSI device to buffer entire maximum

length FDDI frames on-chip for both transmit and receive

simultaneously This allows lower cost systems by enabling

the MACSI device to reside directly on system buses with

high latency requirements

These FIFOs support all of the features available in the orig-

inal BSI device including two transmit and three receive

channels to make efficient use of the FIFO resources New

transmit thresholds are available to allow full use of the larg-

er transmit FIFO

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