DP83256VF datasheet(104/144 Pages) NSC

104 / 144 page

60 Signal Descriptions (Continued)

PHY PORT INTERFACE

The PHY Port Interface consists of IO signals used to connect the PLAYERa device to the Media Access Control (MAC)

sublayer or other PLAYERa device The DP83257 Device has two PHY Port Interfaces The A

Request and A

Indicate paths

from one PHY Port Interface and the B

Request and B

Indicate paths from the second PHY Port Interface Each path

consists of an odd parity bit a control bit and two 4-bit symbols

Refer to section 33 the Configuration Switch for more information

Symbol

Description

AIP

PHY Port A Indicate Parity

A TTL output signal representing odd parity for the 10-bit wide Port A

Indicate signals (AIP AIC and AIDk70l)

AIC

PHY Port A Indicate Control

A TTL output signal indicating that the two 4-bit symbols (AIDk74l and

AIDk30l) are either control symbols (AICe1) or data symbols (AICe0)

AID7

PHY Port A Indicate Data

TTL output signals representing the first 4-bit datacontrol symbol

AID6

AID7 is the most significant bit and AID4 is the least significant bit of the first symbol

AID5

AID4

AID3

PHY Port A Indicate Data

TTL output signals representing the second 4-bit datacontrol symbol

AID2

AID3 is the most significant bit and AID0 is the least significant bit of the second symbol

AID1

AID0

ARP

PHY Port A Request Parity

A TTL input signal representing odd parity for the 10-bit wide Port A

Request signals (ARP ARC and ARDk70l)

ARC

PHY Port A Request Control

A TTL input signal indicating that the two 4-bit symbols

(ARDk74l and ARDk30l) are either control symbols (ARCe1) or data symbols (ARCe0)

ARD7

PHY Port A Request Data

TTL input signals representing the first 4-bit datacontrol symbol

ARD6

ARD7 is the most significant bit and ARD4 is the least significant bit of the first symbol

ARD5

ARD4

ARD3

PHY Port A Request Data

TTL input signals representing the second 4-bit datacontrol symbol

ARD2

ARD3 is the most significant bit and ARD0 is the least significant bit of the second symbol

ARD1

ARD0

BIP

114

PHY Port B Indicate Parity

A TTL output signal representing odd parity for the 10-bit wide Port A

Indicate signals (BIP BIC and BIDk70l)

BIC

112

PHY Port B Indicate Control

A TTL output signal indicating that the two 4-bit symbols (BIDk74l and

BIDk30l) are either control symbols (BICe1) or data symbols (BICe0)

BID7

110

PHY Port B Indicate Data

TTL output signals representing the first 4-bit datacontrol symbol

BID6

108

BID7 is the most significant bit and BID4 is the least significant bit of the first symbol

BID5

106

BID4

102

BID3

100

PHY Port B Indicate Data

TTL output signals representing the second 4-bit datacontrol symbol

BID2

BID3 is the most significant bit and BID0 is the least significant bit of the second symbol

BID1

BID0

BRP

115

PHY Port B Request Parity

A TTL input signal representing odd parity for the 10-bit wide Port A

Request signals (BRP BRC and BRDk70l)

BRC

113

PHY Port B Request Control

A TTL input signal indicating that the two 4-bit symbols

(BRDk74l and BRDk30l) are either control symbols (BRCe1) or data symbols (BRCe0)

104

DP83256VF датащи(PDF) 104 Page - National Semiconductor (TI)

DP83256VF датащи(HTML) 104 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL