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DP83256VF датащи(PDF) 103 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали DP83256VF
подробное описание детали  PLAYERa??Device (FDDI Physical Layer Controller)
PDF  144 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83256VF датащи(HTML) 103 Page - National Semiconductor (TI)

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60 Signal Descriptions (Continued)
Alternate PMD Interface
Symbol
Pin
IO
Description
PMIDa
62
I
PMD Indicate Data
Differential 100k ECL 125 Mbps serial data input signals from the PMD
Receiver into the Clock Recovery Module (CRM) of the PLAYERa
PMIDb
61
RXC
OUTa
56
O
Recovered Clock Out
125 MHz clock recovered by the Clock Recovery Module (CRM) from the
PMID data input
RXC
OUTb
55
These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD
Register (APMDREG) is set to a 1 and are off by default after Reset
When these two pins are not used they should be left Not Connected (NC)
RXD
OUTa
83
O
Recovered Data Out
125 Mbps data recovered by the Clock Recovery Module (CRM) from the
PMID data input
RXD
OUTb
82
These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD
Register (APMDREG) is set to a 1 and are off by default after Reset
When these two pins are not used they should be left Not Connected (NC)
RXC
INa
76
I
Receive Clock In
Clock inputs to the Player section of the PLAYERa These inputs must be
synchronized with the RXD
IN inputs
RXC
INb
75
These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD
Register (APMDREG) is set to a 1 and are off by default after Reset
When these two pins are not used pin 76 should be left Not Connected (NC) and pin 75 should be
connected directly to ground (Reserved
0)
RXD
INa
78
I
Receive Data In
Data inputs to the Player section of the PLAYERa These inputs must be
synchronized with the RXC
IN inputs
RXD
INb
77
These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD
Register (APMDREG) is set to a 1 and are off by default after Reset
When these two pins are not used pin 78 should be left Not Connected (NC) and pin 77 should be
connected directly to ground (Reserved
0)
PMRDa
54
O
PMD Request Data
Differential 100k ECL 125 Mbps serial data output signals to the PMD
transmitter
PMRDb
53
TXCa
51
O
Transmit Clock
125 MHz 100k ECL compatible differential outputs synchronized to the outgoing
PMRD data
TXCb
50
These signals can be enabled using the Transmit Clock Enable (TXCE) bit in the Clock Generation
Module Register (CGMREG)
When these two pins are not used they should be left Not Connected (NC)
SDa
60
I
Signal Detect
Differential 100k ECL input signals from the PMD receiver indicating that a signal
is being received by the PMD receiver
SDb
59
TEL
74
I
PMD Transmitter Enable Level
A TTL input signal to select the PMD transmitter Enable (TXE)
signal level
TXE
73
O
PMD Transmitter Enable
A TTL output signal to enabledisable the PMD transmitter The output
level of the TXE pin is determined by three parameters the Transmit Enable (TE) bit in the Mode
Register the TM2 – TM0 bits in the Current Transmit State Register and the input to the TEL pin
The following rules summarize the output of the TXE pin
1 If TEe0 and TELeGND then TXEeVCC
2 If TEe0 and TELeVCC then TXEeGND
3 If TEe1 and OTM and TELeGND then TXEeVCC
4 If TEe1 and OTM and TELeVCC then TXEeGND
5 If TEe1 and not OTM and TELeGND then TXEeGND
6 If TEe1 and not OTM and TELeVCC then TXEeVCC
103



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