DP83256VF datasheet(92/144 Pages) NSC

92 / 144 page

60 Signal Descriptions (Continued)

CLOCK INTERFACE

The Clock Interface consists of 125 MHz and 25 MHz clocks supplied by the PLAYERa device as well as reference and

feedback inputs

Symbol

Description

LBC1

Local Byte Clock

TTL compatible 125 MHz 50% duty cycle clock outputs which are phase

locked to a crystal oscillator or reference signal The PH

SEL input determines whether the five

LBC2

phase outputs are phase offset by 8 ns or 16 ns

LBC3

LBC4

LBC5

100

SEL

Phase Select

TTL compatible input used to select eithera8nsor16ns phase offset between the 5

local byte clocks (LBC’s) The LBC’s are phase offset 8ns apart when PH

SEL is at a logic LOW

level and 16 ns apart when at a logic HI level

FBK

Feedback Input

TTL compatible input for use as the PLL’s phase comparator feedback input to

close the Phase Locked Loop This input is intended to be driven from one of the Local Byte Clocks

(LBC’s) from the same PLAYERa device

LSC

Local Symbol Clock

TTL compatible 25 MHz output for driving the MACSI or BMAC devices This

output’s negative phase transition is aligned with the LBC1 output transitions and has a 40% HI and

60% LOW duty cycle

CLK16

Clock 1632

TTL compatible clock with a selectable frequency of approximately 15625 MHz or

3125 MHz The frequency can be selected using the Clock Select (CLKSEL) bit of the Mode 2

Note

No glitches appear at the output when switching frequencies

XTAL

External Crystal Oscillator Input

This input in conjunction with the XTAL

OUT output is

designed for use of an external crystal oscillator network as the frequency reference for the clock

generation module’s internal VCO A diagram of the required circuit which includes only a 125 MHz

crystal and 2 loading capacitors is shown in

Figure 3-19

This input is selected when the REF

SEL input is at a logic LOW level When not being used this

input should be tied to ground

XTAL

OUT

External Crystal Oscillator Output

This output in conjunction with the XTAL

IN input is designed

for use of an external crystal oscillator network as the frequency reference for the clock generation

module’s internal VCO A diagram of the required circuit which includes only a 125 MHz crystal and

2 loading capacitors is shown in

Figure 3-19

REF

Reference Input

TTL compatible input for use as the PLL’s phase comparator reference frequency

This input is for use in dual attach station or concentrator configurations where there are multiple

PLAYERa devices at a given site requiring synchronization

This input is selected when the REF

SEL input is at a logic HI level

REF

SEL

Reference Select

TTL compatible input which selects either the crystal oscillator inputs XTAL

and XTAL

OUT or the REF

IN inputs as the reference frequency inputs for the PLL

The crystal oscillator inputs are selected when REF

SEL is at a logic LOW level and the REF

input is selected as the reference when REF

SEL is at a logic HI level

LPFLTR

Loop Filter

This is a diagnostic output that allows monitoring of the clock generation module’s filter

node This output is disabled by default and does not need to be connected to any external device It

can be enabled using the FLTREN bit of the Clock generation module register (CGMREG)

Note

In normal operation this pin should be disabled

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