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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83256VF датащи(PDF) 73 Page - National Semiconductor (TI) |
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DP83256VF датащи(HTML) 73 Page - National Semiconductor (TI) |
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73 / 144 page  50 Registers (Continued) 529 RECEIVE CONDITION COMPARISON REGISTER A (RCCRA) The Receive Condition Comparison Register A ensures that the Control Bus must first read a bit modified by the PLAYERa device before it can be written to by the Control Bus Interface The current state of RCRA is automatically written into the Receive Condition Comparison Register A (ie RCCRAeRCRA) during a Control Bus Interface read cycle of RCRA During a Control Bus Interface write cycle the PLAYERa device will set the Conditional Write Inhibit bit (CWI) of the Interrupt Condition Register (ICR) to 1 and prevent the setting or clearing of a bit within RCRA when the value of a bit in RCRA differs from the value of the corresponding bit in the Receive Condition Comparison Register A ACCESS RULES ADDRESS READ WRITE 1Ch Always Always D7 D6 D5 D4 D3 D2 D1 D0 LSUPIC LSCC NTC NLSC MLSC HLSC QLSC NSDC Bit Symbol Description D0 NSDC NO SIGNAL DETECT COMPARISON The comparison bit for the No Signal Detect bit (NSD) of the Receive Condition Register A (RCRA) D1 QLSC QUIET LINE STATE COMPARISON The comparison bit for the Quiet Line State bit (QLS) of the Receive Condition Register A (RCRA) D2 HLSC HALT LINE STATE COMPARISON The comparison bit for the Halt Line State bit (HLS) of the Receive Condition Register A (RCRA) D3 MLSC MASTER LINE STATE COMPARISON The comparison bit for the Master Line State bit (MLS) of the Receive Condition Register A (RCRA) D4 NLSC NOISE LINE STATE COMPARISON The comparison bit for the Noise Line State bit (NLS) of the Receive Condition Register A (RCRA) D5 NTC NOISE THRESHOLD COMPARISON The comparison bit for the Noise Threshold bit (NT) of the Receive Condition Register A (RCRA) D6 LSCC LINE STATE CHANGE COMPARISON The comparison bit for the Line State Change bit (LSC) of the Receive Condition Register A (RCRA) D7 LSUPIC LINE STATE UNKNOWN AND PHY INVALID COMPARISON The comparison bit for the Line State Unknown and PHY Invalid bit (LSUPI) of the Receive Condition Register A (RCRA) 73 |
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