DP83256 datasheet(108/144 Pages) NSC

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60 Signal Descriptions (Continued)

MISCELLANEOUS INTERFACE

The Miscellaneous Interface consist of a reset signal user definable sense signals and user definable enable signals

Symbol

Description

RST

116

Reset

An active low TTL input signal which clears all registers The signal must be kept asserted for a

minimum amount of time Once the ERST signal is asserted the PLAYERa device should be allowed

the specified amount of time to reset internal logic Note that bit zero of the Mode Register will be set to

zero (ie Stop Mode) See section 42 Stop Mode of Operation for more information

SP0

User Definable Sense Pin 0

A TTL input signal from a user defined source Sense Bit 0 (SB0) of the

User Definable Register (UDR) will be set to one if the signal is asserted for a minimum of 160 ns Once

the asserted signal is latched Sense Bit 0 can only be cleared through the Control Bus Interface even if

the signal is deasserted This ensures that the Control Bus Interface will record the source of events

which can cause interrupts

SP1

User Definable Sense Pin 1

A TTL input signal from a user defined source Sense Bit 1 (SB1) of the

User Definable Register (UDR) will be set to one if the signal is asserted for a minimum of 160 ns Once

the asserted signal is latched Sense Bit 1 can only be cleared through the Control Bus Interface even if

the signal is deasserted This ensures that the Control Bus Interface will record the source of events

which can cause interrupts

SP2

User Definable Sense Pin 2

A TTL input signal from a user defined source Sense Bit 2 (SB2) of the

User Definable Register (UDR) will be set to one if the signal is asserted for a minimum of 160 ns Once

the asserted signal is latched Sense Bit 2 can only be cleared through the Control Bus Interface even if

the signal is deasserted This ensures that the Control Bus Interface will record the source of events

which can cause interrupts

EP0

User Definable Enable Pin 0

A TTL output signal allowing control of external logic through the Control

Bus Interface EP0 is asserteddeasserted through Enable Bit 0 (EB0) of the User Definable Register

(UDR) When Enable Bit 0 is set to zero EP0 is deasserted When Enable Bit 0 is set to one EP0 is

asserted

EP1

User Definable Enable Pin 1

A TTL output signal allowing control of external logic through the Control

Bus Interface EP1 is asserteddeasserted through Enable Bit 1 (EB1) of the User Definable Register

(UDR) When Enable Bit 1 is set to zero EP1 is deasserted When Enable Bit 1 is set to one EP1 is

asserted

EP2

User Definable Enable Pin 2

A TTL output signal allowing control of external logic through the Control

Bus Interface EP2 is asserteddeasserted through Enable Bit 2 (EB2) of the User Definable Register

(UDR) When Enable Bit 2 is set to zero EP2 is deasserted When Enable Bit 2 is set to one EP2 is

asserted

Cascade Start

A TTL input signal used to synchronize cascaded PLAYERa devices in point-to-point

applications

The signal is asserted when all of the cascaded PLAYERa devices have the Cascade Mode (CM) bit of

the Mode Register (MR) set to one and all of the Cascade Ready (CR) pins of the cascaded PLAYERa

devices have been released

When Cascade Mode is not being used this input should be tied to Ground

For further information refer to section 44 Cascade Mode of Operation

Cascade Ready

An Open Drain output signal used to synchronize cascaded PLAYERa devices in

point-to-point applications

The signal is released (ie an Open Drain line is released) when all the cascaded PLAYERa devices

have the Cascade Mode (CM) bit of the Mode Register (MR) is set to one and a JK symbol pair has been

received

When Cascade Mode is not being used this input should be left Not Connected (NC)

For further information refer to section 44 Cascade Mode of Operation

108

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