DP83256 datasheet(91/144 Pages) NSC

91 / 144 page

60 Signal Descriptions (Continued)

CONTROL BUS INTERFACE

The Control Bus Interface consists of IO signals used to connect the PLAYERa device to Station Management (SMT)

The Control Bus is an asynchronous interface between the PLAYERa device and a general purpose microprocessor or other

controller It provides access to 64 8-bit internal registers

In the PLAYERa device the Control Bus address range has been expanded by 1-bit to 6 bits of address space

Symbol

Description

Control Enable

An active-low TTL input signal which enables the Control Bus port for a read or write

cycle R EW CBAk50l CBP and CBDk70l must be valid at the time ECE is low

R EW72

Read EWrite

A TTL input signal which indicates a read Control Bus cycle(R EWe1) or a write

Control Bus cycle (R EWe0)

ACK

Acknowledge

An active low TTL open drain output signal which indicates the completion of a read

or write cycle During a read cycle CBDk70l are valid as long as EACK is low (EACKe0) During a

write cycle a microprocessor must hold CBDk70l valid until EACK becomes low Once EACK is low

it will remain low as long as ECE remains low (ECEe0)

INT

Interrupt

An active low open drain TTL output signal indicating that an interrupt condition has

occurred The Interrupt Condition Register (ICR) should be read in order to find out the source of the

interrupt Interrupts can be masked through the use of the Interrupt Condition Mask Register (ICMR)

CBA5

Control Bus Address

TTL input signals used to select the address of the register to be read or written

CBA4

CBA5 is the most significant bit (MSB) and CBA0 is the least significant bit (LSB) of the address signals

CBA3

CBA2

CBA1

CBA0

CBP

Control Bus Parity

A bidirectional TTL signal representing odd parity for the Control Bus data

(CBDk70l)

During a read cycle the signal is held valid by the PLAYERa device as long as EACK is low

During a write cycle the signal must be valid when ECE is low and must be held valid until EACK

becomes low If incorrect parity is used during a write cycle the PLAYERa device will inhibit the write

cycle and set the Control Bus Data Parity Error (CPE) bit in the Interrupt Condition Register (ICR)

CBD7

Control Bus Data

Bidirectional TTL signals containing the data to be read from or written to a register

CBD6

During a read cycle the signal is held valid by the PLAYERa device as long as EACK is low

CBD5

During a write cycle the signal must be valid when ECE is low and must be held valid until EACK

CBD4

becomes low

CBD3

CBD2

CBD1

CBD0

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