DP83256 datasheet(57/144 Pages) NSC

57 / 144 page

50 Registers (Continued)

513 RECEIVE CONDITION MASK REGISTER B (RCMRB)

The Receive Condition Mask Register B allows the user to dynamically select which events will generate an interrupt

The Receive Condition B bit (RCB) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the

Receive Condition Register B (RCRA) is set to 1 and the corresponding mask bits in this register is also set to 1

Since this register is cleared (ie set to 0) during the reset process all interrupts are initially masked

ACCESS RULES

ADDRESS

READ

WRITE

0Ch

Always

RESM

SILSM

EBOUM

CSEM

LSUPVM

ALSM

STM

ILSM

Bit

Symbol

Description

ILSM

IDLE LINE STATE MASK

The mask bit for the Idle Line State bit (ILS) of the Receive Condition Register B

(RCRB)

STM

STATE THRESHOLD MASK

The mask bit for the State Threshold bit (ST) of the Receive Condition Register B

(RCRB)

ALSM

ACTIVE LINE STATE MASK

The mask bit for the Active Line State bit (ALS) of the Receive Condition Register

B (RCRB)

LSUPVM

LINE STATE UNKNOWN AND PHY VALID MASK

The mask bit for the Line State Unknown and PHY Valid bit

(LSUPV) of the Receive Condition Register B (RCRB)

CSEM

CASCADE SYNCHRONIZATION ERROR MASKCONNECTION SERVICE EVENT MASK

The mask bit for the Cascade Synchronization ErrorConnection service event bit (CSE) of the Receive Condition

EBOUM

ELASTICITY BUFFER OVERFLOWUNDERFLOW MASK

The mask bit for the Elasticity Buffer Overflow

Underflow bit (EBOU) of the Receive Condition Register B (RCRB)

SILSM

SUPER IDLE LINE STATE MASK

The mask bit for the Super Idle Line State bit (SILS) of the Receive Condition

RESM

RESERVED MASK

The mask bit for the Reserved bit (RES) of the Receive Condition Register B (RCRB)

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