DP83256 datasheet(24/144 Pages) NSC

24 / 144 page

30 Functional Description (Continued)

The voltage on the Loop Filter is set by the current pulses

generated by the Phase Comparator The voltage on the

Loop Filter node controls the frequency of the 250 MHz

VCO

250 MHZ VOLTAGE CONTROLLED OSCILLATOR (VCO)

The internal Voltage Controlled Oscillator is a low gain VCO

whose primary frequency of oscillation centers around

250 MHz The VCO produces little clock jitter due to its

exceptional stability under all circumstances

The VCO’s output frequency is proportional to the voltage

on the Loop Filter node

OUTPUT PHASING

The Output Phasing block is a precision clock division circuit

that produces clock signals of 4 distinct frequencies Within

the 125 MHz frequency 5 clock signals with selectable 8 ns

or 16 ns phase difference are produced

The following clock signals are produced

System Clock (CLK16CLK32)

Local Symbol Clock (LSC)

Local Byte Clocks 1 – 5 (LBCn) (Divide by 10)

System Clock (CLK16CLK32)

The System Clock is provided as an extra set of clock fre-

quencies that may be used as a clock for non-FDDI chipset

portions of a system or as a higher frequency System Inter-

face clock for the MACSI device This clock is derived by

dividing the 125 MHz clock by 8 or 4 times

The frequency is selectable through the CLKSEL bit of the

MODE2 register The output has built-in glitch suppression

so that changing the CLKSEL bit will not result in glitches

appearing at the output

Local Symbol Clock (LSC)

The Local Symbol Clock is a 40% HIGH60% LOW duty

cycle clock provided for use by the MACSI device and any

external logic that needs to be synchronized to the Symbol

timing

This clock is derived by dividing the 125 MHz clock by 5

Local Byte Clocks 1 – 5 (LBCn)

The Local Byte Clocks are provided for use by the MACSI

device by any external logic that needs to be synchronized

to the Byte timing and for use in concentrators to synchro-

nize the timing between multiple PLAYERa devices

These clocks are derived by dividing the 125 MHz clock by

10 The different phase relationships between the LBCs are

achieved by tapping off of different outputs of a Johnson

counter inside the Output Phasing block

The phase relationship (separation by 8 ns or 16 ns) of the

LBCs is selected using the PH

SEL pin

One of the LBCs must be used as the source of the feed-

back input FBK

IN which requires a 125 MHz frequency

When the PLAYERa device is using a crystal as a refer-

ence it does not matter which LBC is used as the feedback

input Typically the least loaded LBC is used However

when using an external reference that is supplied by anoth-

er PLAYERa device it is important to select the LBC that

keeps your system properly synchronized Typically all de-

vices will use LBC1 as the feedback input

36 STATION MANAGEMENT SUPPORT

The Station Management Support Block provides a number

of useful features to simplify the implementation of the Con-

nection Management (CMT) portion of SMT

These features eliminate the most severe CMT response

time constraints imposed by the PC

React and CF

React

times The many integrated counters and timers also elimi-

nate the need for additional external devices

The following CMT features are supported

PC React

CF React

Auto Scrubbing (TCF Timer)

Timer Idle Detection (TID Timer)

Noise Event Counter (TNE Timer)

Link Error Monitor (LEM Counter)

REACT

React is one of the timing restrictions imposed by Con-

nection Management (CMT) It is one of the two most crit-

ical timing restrictions imposed (the other being CF

Re-

act)

The ANSI SMT standard states that ‘‘PC

React is the max-

imum time for PCM Physical Connection Management to

make a state transition to PC

Break when QLS a fault

condition or PC

Start signal is present This maximum

time also places a limit on the time to react to a PC

Stop

signal This limitation does not apply to any other PCM tran-

sitions’’ PC

React puts a sharp time limit on how long it

takes to transition to the PC

Break state and transmit the

correct line state when a PC

Break transition is required

The range for the timer is PC

React s 30 ms and has a

default value equal to 30 ms

The PLAYERa device contains a Trigger Definition Regis-

ter and a set of CMT Condition Registers that can be used

to satisfy the PC

React timing

The Trigger Definition Register (TDR) controls two func-

tions First it allows the selection of the line state(s) on

which to trigger (SILS MLS HLS

) For PC

React the

line states used would be the ones that caused a transition

to the PC

Break state from the current PCM state

Second it allows specification of a line state to be transmit-

ted when the trigger condition is met For PC

React this is

the line state that needs to be transmitted when a transition

to the PC

Break state occurs which is Quiet Line State

(QLS)

The set of CMT Condition registers controls interrupt gener-

ation when a trigger condition occurs The CMT Condition

CMT Condition Comparison Register (CMTCCR) and a

CMT Condition Mask Register (CMTCMR)

Line state triggering for PC

React is enabled by selecting

line states to trigger on from the Trigger Definition Register

(TDR) bits 3-7

The Trigger Condition Occurred (TCO) bit of the CMTCR is

automatically set when the trigger condition specified by the

TDR register is met

The line state specified by the Trigger Definition Register

(TDR) bits 0 – 2 is then loaded into the Current Transmit

Mode Register (CTSR) causing the line state to be trans-

mitted

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