COP884CF datasheet(14/44 Pages) NSC

14 / 44 page

Pin Descriptions (Continued)

Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input

pin (G6), and two dedicated output pins (G1 and G7). Pins

G0 and G2–G6 all have Schmitt Triggers on their inputs. Pin

G1 serves as the dedicated WDOUT WatchDog output,

while pin G7 is either input or output depending on the oscil-

lator mask option selected. With the crystal oscillator option

selected, G7 serves as the dedicated output pin for the CKO

clock output. With the single-pin R/C oscillator mask option

selected, G7 serves as a general purpose input pin, but is

also used to bring the device out of HALT mode with a low to

high transition on G7. There are two registers associated

with the G Port, a data register and a configuration register.

Therefore, each of the 5 I/O bits (G0, G2–G5) can be indi-

vidually configured under software control.

Since G6 is an input only pin and G7 is the dedicated CKO

clock output pin or general purpose input (R/C clock configu-

ration), the associated bits in the data and configuration reg-

isters for G6 and G7 are used for special purpose functions

as outlined below. Reading the G6 and G7 data bits will re-

turn zeros.

Note that the chip will be placed in the HALT mode by writing

a “1” to bit 7 of the Port G Data Register. Similarly the chip

will be placed in the IDLE mode by writing a “1” to bit 6 of the

Port G Data Register.

Writing a “1” to bit 6 of the Port G Configuration Register en-

ables the MICROWIRE/PLUS to operate with the alternate

phase of the SK clock. The G7 configuration bit, if set high,

enables the clock start up delay after HALT when the R/C

clock configuration is used.

Config Reg.

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

Port G has the following alternate features:

SI (MICROWIRE™ Serial Data Input)

SK (MICROWIRE Serial Clock)

SO (MICROWIRE Serial Data Output)

T1A (Timer T1 I/O)

T1B (Timer T1 Capture Input)

INTR (External Interrupt Input)

Port G has the following dedicated functions:

CKO Oscillator dedicated output or general purpose

input

WDOUT WATCHDOG and/or Clock Monitor dedicated

output.

Port C is an 8-bit I/O port. The 40-pin device does not have

a full complement of Port C pins. The unavailable pins are

not terminated. A read operation for these unterminated pins

will return unpredictable values.

Port I is an 8-bit Hi-Z input port, and also provides the analog

inputs to the A/D converter. The 28-pin device does not have

a full complement of Port I pins. The unavailable pins are not

terminated (i.e. they are floating). A read operation from

these unterminated pins will return unpredictable values.

The user should ensure that the software takes this into ac-

count by either masking out these inputs, or else restricting

the accesses to bit operations only. If unterminated, Port I

pins will draw power only when addressed.

Port D is an 8-bit output port that is preset high when RESET

goes low. The user can tie two or more D port outputs (ex-

cept D2) together in order to get a higher drive.

Note: Care must be exercised with the D2 pin operation. At RESET, the ex-

ternal loads on this pin must ensure that the output voltages stay

above 0.8 VCC to prevent the chip from entering special modes. Also

keep the external loading on D2 to less than 1000 pF.

Functional Description

The architecture of the device is modified Harvard architec-

ture. With the Harvard architecture, the control store pro-

gram memory (ROM) is separated from the data store

memory (RAM). Both ROM and RAM have their own sepa-

rate addressing space with separate address buses. The ar-

chitecture, though based on Harvard architecture, permits

transfer of data from ROM to RAM.

CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift

operation in one instruction (t

c) cycle time.

There are five CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally

post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be

optionally post auto incremented or decremented.

SP is the 8-bit stack pointer, which points to the subroutine/

interrupt stack (in RAM). The SP is initialized to RAM ad-

dress 06F with reset.

All the CPU registers are memory mapped with the excep-

tion of the Accumulator (A) and the Program Counter (PC).

PROGRAM MEMORY

Program memory consists of 4096 bytes of ROM. These

bytes may hold program instructions or constant data (data

tables for the LAID instruction, jump vectors for the JID in-

struction, and interrupt vectors for the VIS instruction). The

program memory is addressed by the 15-bit program

counter (PC). All interrupts vector to program memory loca-

tion 0FF Hex.

DATA MEMORY

The data memory address space includes the on-chip RAM

and data registers, the I/O registers (Configuration, Data and

Pin), the control registers, the MICROWIRE/PLUS SIO shift

with the timers (with the exception of the IDLE timer). Data

memory is addressed directly by the instruction or indirectly

by the B, X and SP pointers.

The device has 128 bytes of RAM. Sixteen bytes of RAM are

mapped as “registers” at addresses 0F0 to 0FF Hex. These

registers can be loaded immediately, and also decremented

and tested with the DRSZ (decrement register and skip if

zero) instruction. The memory pointer registers X, SP, and B

are memory mapped into this space at address locations

0FC to 0FE Hex respectively, with the other registers (other

than reserved register 0FF) being available for general us-

age.

The instruction set permits any bit in memory to be set, reset

or tested. All I/O and registers (except A and PC) are

memory mapped; therefore, I/O bits and register bits can be

directly and individually set, reset and tested. The accumula-

tor (A) bits can also be directly and individually tested.

Note: RAM contents are undefined upon power-up.

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