COP884CF datasheet(33/44 Pages) NSC

33 / 44 page

MICROWIRE/PLUS (Continued)

MICROWIRE/PLUS Slave Mode Operation

In the MICROWIRE/PLUS Slave mode of operation the SK

clock is generated by an external source. Setting the MSEL

bit in the CNTRL register enables the SO and SK functions

onto the G Port. The SK pin must be selected as an input

and the SO pin is selected as an output pin by setting and re-

setting the appropriate bit in the Port G configuration regis-

ter.

Table 8 summarizes the settings required to enter the

Slave mode of operation.

TABLE 8. MICROWIRE/PLUS Mode Settings

This table assumes that the control flag MSEL is set.

G4 (SO)

G5 (SK)

Operation

Config. Bit

Fun.

Int.

MICROWIRE/PLUS

Master

TRI-

Int.

MICROWIRE/PLUS

STATE

Master

Ext.

MICROWIRE/PLUS

Slave

TRI-

Ext.

MICROWIRE/PLUS

STATE

Slave

The user must set the BUSY flag immediately upon entering

the Slave mode. This will ensure that all data bits sent by the

Master will be shifted properly. After eight clock pulses the

BUSY flag will be cleared and the sequence may be re-

peated.

Alternate SK Phase Operation

The device allows either the normal SK clock or an alternate

phase SK clock to shift data in and out of the SIO register. In

both the modes the SK is normally low. In the normal mode

data is shifted in on the rising edge of the SK clock and the

data is shifted out on the falling edge of the SK clock. The

SIO register is shifted on each falling edge of the SK clock in

the normal mode. In the alternate SK phase mode the SIO

A control flag, SKSEL, allows either the normal SK clock or

the alternate SK clock to be selected. Resetting SKSEL

causes the MICROWIRE/PLUS logic to be clocked from the

normal SK signal. Setting the SKSEL flag selects the alter-

nate SK clock. The SKSEL is mapped into the G6 configura-

tion bit. The SKSEL flag will power up in the reset condition,

selecting the normal SK signal.

Memory Map

All RAM, ports and registers (except A and PC) are mapped

into data memory address space

Address

Contents

00 to 6F

On-Chip RAM bytes

70 to BF

Unused RAM Address Space

Timer T2 Lower Byte

Timer T2 Upper Byte

Timer T2 Autoload Register T2RA Lower Byte

Timer T2 Autoload Register T2RA Upper Byte

Timer T2 Autoload Register T2RB Lower Byte

Timer T2 Autoload Register T2RB Upper Byte

Timer T2 Control Register

WATCHDOG Service Register (Reg:WDSVR)

MIWU Edge Select Register (Reg:WKEDG)

MIWU Enable Register (Reg:WKEN)

MIWU Pending Register (Reg:WKPND)

A/D Converter Control Register (Reg:ENAD)

A/D Converter Result Register (Reg: ADRSLT)

CD to

Reserved

Port L Data Register

Port L Configuration Register

Port L Input Pins (Read Only)

Reserved for Port L

Port G Data Register

Port G Configuration Register

Port G Input Pins (Read Only)

Port I Input Pins (Read Only)

Port C Data Register

Port C Configuration Register

Port C Input Pins (Read Only)

Reserved for Port C

Port D Data Register

DD to

Reserved for Port D

E0 to E5

Reserved

Timer T1 Autoload Register T1RB Lower Byte

Timer T1 Autoload Register T1RB Upper Byte

ICNTRL Register

MICROWIRE Shift Register

Timer T1 Lower Byte

Timer T1 Upper Byte

Timer T1 Autoload Register T1RA Lower Byte

Timer T1 Autoload Register T1RA Upper Byte

CNTRL Control Register

PSW Register

F0 to FB

On-Chip RAM Mapped as Registers

X Register

SP Register

B Register

Reserved

Note: Reading memory locations 70-7F Hex will return all ones. Reading

other unused memory locations will return undefined data.

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