CS8900A datasheet(47/128 Pages) CIRRUS

47 / 128 page

DS271PP3

CS8900A

Crystal LAN™ ISA Ethernet Controller

CIRRUS LOGIC PRODUCT DATA SHEET

4.4 Status and Control Registers

The Status and Control registers are the primary

registers used to control and check the status of the

CS8900A. They are organized into two groups:

Configuration/Control Registers and Status/Event

Registers. All Status and Control Registers are 16-

bit words as shown in Figure 16. Bit 0 indicates

whether it is a Configuration/Control Register

(Bit 0 = 1) or a Status/Event Register (Bit 0 = 0).

Bits 0 through 5 provide an internal address code

that describes the exact function of the register.

Bits 6 through F are the actual Configuration/Con-

trol and Status/Event bits.

4.4.1 Configuration and Control Registers

Configuration and Control registers are used to set-

up the following:

•

how frames will be transmitted and received;

•

which frames will be transmitted and received;

•

which events will cause interrupts to the host

processor; and,

•

how the Ethernet physical interface will be

configured.

These registers are read/write and are designated

by odd numbers (e.g. Register 1, Register 3, etc.).

The Transmit Command Register (TxCMD) is a

special type of register. It appears in two separate

locations in the PacketPage memory map. The first

location, PacketPage base + 0108h, is within the

block of Configuration/Control Registers and is

read-only. The second location, PacketPage base +

0144h, is where the actual transmit commands are

issued and is write-only. See Section 4.4.4 on

page 49 (Register 9) and Section 5.7 on page 99 for

a more detailed description of the TxCMD register.

4.4.2 Status and Event Registers

Status and Event registers report the status of trans-

mitted and received frames, as well as information

about the configuration of the CS8900A. They are

read-only and are designated by even numbers (e.g.

The Interrupt Status Queue (ISQ) is a special type

of Status/Event register. It is located at PacketPage

base + 0120h and is the first register the host reads

when responding to an Interrupt.

A more detailed description of the ISQ can be

found in Section 5.1 on page 79.

Three 10-bit counters are included with the Status

and Event registers. RxMISS counts missed re-

ceive frames, TxCOL counts transmit collisions,

and TDR is a time domain reflectometer useful in

locating cable faults. The following sections con-

tain more information about these counters.

Table 13 provides a summary of PacketPage Reg-

ister types.

4.4.3 Status and Control Bit Definitions

This section provides a description of the special

bit types used in the Status and Control registers.

10 Register Bits

1 = Control/Configuration

0 = Status/Event

Internal Address

(bits 0 - 5)

16-bit Register Word

Bit Number

F E

Figure 16. Status and Control Register Format

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