CS8900A datasheet(4/128 Pages) CIRRUS

4 / 128 page

DS271PP3

CS8900A

Crystal LAN™ ISA Ethernet Controller

CIRRUS LOGIC PRODUCT DATA SHEET

3.10.4 Interface Selection ................................................................................................................... 35

3.10.4.1 10BASE-T Only .............................................................................................................. 35

3.10.4.2 AUI Only ......................................................................................................................... 35

3.10.4.3 Auto-Select ..................................................................................................................... 35

3.11 10BASE-T Transceiver...................................................................................................................... 35

3.11.1 10BASE-T Filters ..................................................................................................................... 35

3.11.2 Transmitter............................................................................................................................... 36

3.11.3 Receiver................................................................................................................................... 36

3.11.3.1 Squelch Circuit ............................................................................................................... 36

3.11.3.2 Extended Range............................................................................................................. 36

3.11.4 Link Pulse Detection ................................................................................................................ 36

3.11.5 Receive Polarity Detection and Correction .............................................................................. 37

3.11.6 Collision Detection ................................................................................................................... 37

3.12 Attachment Unit Interface (AUI) ........................................................................................................ 37

3.12.1 AUI Transmitter........................................................................................................................ 37

3.12.2 AUI Receiver............................................................................................................................ 38

3.12.3 Collision Detection ................................................................................................................... 38

3.13 External Clock Oscillator ................................................................................................................... 38

4.0 PACKETPAGE ARCHITECTURE ............................................................................................................ 39

4.1 PacketPage Overview ......................................................................................................................... 39

4.1.1 Integrated Memory..................................................................................................................... 39

4.1.2 Bus Interface Registers ............................................................................................................. 39

4.1.3 Status and Control Registers ..................................................................................................... 39

4.1.4 Initiate Transmit Registers ......................................................................................................... 39

4.1.5 Address Filter Registers............................................................................................................. 39

4.1.6 Receive and Transmit Frame Locations .................................................................................... 39

4.2 PacketPage Memory Map ................................................................................................................... 40

4.3 Bus Interface Registers ....................................................................................................................... 42

4.3.1 Product Identification Code ....................................................................................................... 42

4.3.2 I/O Base Address ...................................................................................................................... 42

4.3.3 Interrupt Number ....................................................................................................................... 43

4.3.4 DMA Channel Number .............................................................................................................. 43

4.3.5 DMA Start of Frame .................................................................................................................. 44

4.3.6 DMA Frame Count ................................................................................................................... 44

4.3.7 RxDMA Byte Count .................................................................................................................. 44

4.3.8 Memory Base Address .............................................................................................................. 44

4.3.9 Boot PROM Base Address ....................................................................................................... 45

4.3.10 Boot PROM Address Mask ..................................................................................................... 45

4.3.11 EEPROM Command ............................................................................................................... 46

4.3.12 EEPROM Data ........................................................................................................................ 46

4.3.13 Receive Frame Byte Counter .................................................................................................. 46

4.4 Status and Control Registers .............................................................................................................. 47

4.4.1 Configuration and Control Registers.......................................................................................... 47

4.4.2 Status and Event Registers ....................................................................................................... 47

4.4.3 Status and Control Bit Definitions .............................................................................................. 47

4.4.3.1 Act-Once Bits ................................................................................................................... 48

4.4.3.2 Temporal Bits ................................................................................................................... 48

4.4.3.3 Interrupt Enable Bits and Events...................................................................................... 48

4.4.3.4 Accept Bits ....................................................................................................................... 48

4.4.4 Status and Control Register Summary ......................................................................................49

4.4.5 Register 0: Interrupt Status Queue .......................................................................................... 52

4.4.6 Register 3: Receiver Configuration .......................................................................................... 53

4.4.7 Register 4: Receiver Event ...................................................................................................... 54

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