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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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Z80 датащи(PDF) 68 Page - Zilog, Inc. |
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Z80 датащи(HTML) 68 Page - Zilog, Inc. |
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68 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access port’s Ready line goes inactive before this occurs, the DMA pauses until the Ready line comes active again. This is also called Block mode. In all modes, the operation on the byte is completed in an orderly fashion when a byte of data is read into the DMA, regardless of the state of other signals (including a port’s Ready line). Figure 20 illustrates the sequence of events that occur in a sequential transfer/search of one byte, whatever of the mode of operation. First, the source port address is incremented or decre- mented, if it was programmed to be a variable-address port. Then, the byte is read from that port to the DMA. Next, the destination port address is incremented or decremented, if it was programmed to be a variable. The byte is then written to the destination port. If a search capability is included, the byte is compared to the match byte. When no byte match occurs, the DMA increments the byte counter and continues. When a byte is found, a status bit is set and the DMA either continues by incrementing the byte counter, stops (releases the bus), or interrupts the CPU, depending on its initial programming. The next three figures illustrate how the three modes function before, during, and after the single-byte operation, which is shown in Figure 20. Operation in the Byte mode (Figure 21) begins with an enabling command from the CPU and a test of the I/O device’s Ready line. When the Ready line is active, the DMA requests the system bus (address, data, and control buses) through the Bus Request line, and the CPU acknowledges and releases control to the DMA. The transfer of and/or search of one byte takes place as in Figure 20. Then, a test is made for end-of-block by checking to see if the byte counter has reached the programmed block length. If the end is not reached, the DMA releases the bus back to the CPU. If the end is reached, a status bit is set and some terminating action occurs, according to the initial programming. Releasing the bus between each byte allows the CPU to execute at least one machine cycle before releasing the bus again to the DMA for the next byte transfer. This means that while the DMA operates more slowly than it could in other modes, CPU activities like interrupt acknowledgement, polling, and memory refresh can be inter- leaved with DMA transfers in the Byte mode. |
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