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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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Z80 датащи(PDF) 53 Page - Zilog, Inc. |
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Z80 датащи(HTML) 53 Page - Zilog, Inc. |
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53 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access • The I/O device interrupts the CPU and the block transfer instruction is executed in the CPU interrupt service routine. This method has a response time of at least 5 to 10 µs, even in 4 MHz Z80A and Z8000 devices. • The CPU begins executing the device service routine before the I/O device is ready, and a flag bit is constantly polled by the CPU. When the flag bit indicates that the device is ready, the CPU jumps to the block transfer instruction. This method sometimes produces a response time of less than 5 µs, but it uses the entire capability of the CPU. • The CPU begins executing the block transfer instruction in an interrupt service routine before the I/O device is actually ready. The I/O device idles the CPU with the Wait line just after the Read and Chip-Select lines become active. When the I/O device is ready, it releases the wait line and the transfer is completed. This method gives the best response time (250 ns in a 4 MHz Z80A or Z8000 CPU) but ties up the bus. Both transfer and response times on most CPUs are often too slow. While transfer speed can be quite high with the Z80 and Z8000 CPUs, the response time can be too long in interrupt-driven transfer situations. DMA Data Transfers A DMA controller (DMAC) performs direct data transfers between the source and destination without going through the CPU, and without the instruction fetches required by the CPU. It performs all of the steps illus- trated in Figure 15 through hardware. for example, in a memory-to-I/O transfer, the starting address in memory and the length of the block to be transferred are written to the DMA by the CPU before to the transfer. The DMAC begins transferring data when the CPU enables theDMACand theReady lineI/O of thedevicebecomes active. In most cases, the CPU is idle during a DMA transfer. When the transfer is complete, the DMAC signals the CPU and releases control. |
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