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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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Z80 датащи(PDF) 25 Page - Zilog, Inc. |
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Z80 датащи(HTML) 25 Page - Zilog, Inc. |
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25 / 330 page  < %27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Counter/Timer Channels Interrupt Control Logic The Interrupt Control Logic insures that the CTC acts in accordance with Z80 system interrupt protocol for Nested Priority Interrupting and Return From Interrupt. The priority of any system device is determined by its physical location in a daisy-chain configuration. Two signal lines, CIEI and IEO, are provided in CTC devices to form this system daisy-chain. The device closest to the CPU has the highest priority. Within the CTC, interrupt priority is predetermined by channel number, with Channel 0 having highest and Channel 3 the lowest priority. See Table 3. The purpose of a CTC-generated interrupt, as with any peripheral device, is to force the CPU to execute an interrupt service routine. According to Z80 system interrupt protocol, lower priority devices or channels may not interrupt higher priority devices or channels that have not had their interrupt service routines completed. However, high priority devices or channels may interrupt the servicing of lower priority devices or channels. Table 3. Interrupt Vector Register 765 4321 0 Supplied by User Channel Identifier Word R/W R/W R/W Bit Number Field R/W Value Description 7–3 Reserved R/W Supplied by User 2–1 Channel Identifier (Automatically inserted by CTC) R/W 11 10 01 00 Channel 3 Channel 2 Channel 1 Channel 0 0Word R/W 1 0 Control Interrupt Vector |
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