AD6676EBZ datasheet(27/90 Pages) AD

27 / 90 page

Data Sheet

AD6676

Rev. A | Page 27 of 90

Σ-Δ ADC Overload and Recovery

The Σ-Δ ADC is a sixth-order modulator employing negative

feedback to reduce the noise contribution of its internal quantizer.

Like any ADC, the quantizer is driven into overload under large

signal conditions, causing its output to be a poor representation

of its input. However, unlike traditional ADCs that operate in

open-loop, a Σ-Δ ADC can be driven into overload with signals

slightly below its 0 dBFS full-scale input level and the feedback

loop can become unstable and may not return to normal operation

when the overload condition is removed. A typical unstable Σ-Δ

ADC produces a digital output that varies between plus or minus

full scale. The AD6676 employs several techniques to solve

these problems.

First, to make the no overload range with continuous wave

tones approach levels near 0 dBFS, the AD6676 uses a 5-bit

quantizer. The AD6676 is specified to remain unconditionally

stable for continuous wave levels below −2 dBFS over its full

operation range, with a typical overload level of −0.5 dBFS. In

practice, the large signal waveform characteristics that determine

the occurrence and duration of its peaks affect the overload

threshold. A continuous wave tone is close to the worst-case

scenario for overload because the peak levels have the highest

probability of occurrence. Alternatively, a signal that has a much

higher crest factor and a more Gaussian-like histogram is less

likely to cause overload due to the short duration of its peak

excursions. For this reason, for systems employing AGC, consider

the waveform characteristics when setting the AGC threshold.

Second, to ensure that the ADC does not become stuck in a self

sustaining overload condition, the AD6676 includes the means

to detect overload, reset the Σ-Δ ADC, and quickly return it to

normal operation. An overload condition is declared if more

than five out of eight samples from the quantizer are equal to a

positive or negative full-scale value. After overload is detected,

the internal nodes within the Σ-Δ ADC are reset to their zero

state and the attenuation setting is temporarily increased by

6 dB. The ADC reset is removed after 16 FADC clock cycles and

over the next 48 FADC clock cycles, the attenuation is returned

to its original value. If the input signal is such that an overload

occurs again, this process repeats until the signal falls within

the no overload range of the Σ-Δ ADC. Although the Σ-Δ

ADC produces good data within 64 FADC clock cycles of the

signal falling within the no overload range, the bad data

associated with an overload event must be flushed out of the

decimation filters before the output of the AD6676 is completely

clean of any memory effects.

Figure 76 to Figure 79 show the measured overload recovery

response for each of the decimation filter modes (DEC_MODE)

when driven by a periodic pulsed CW waveform of 10 ns duration

and 2% duty cycle. The narrow pulse region of the waveform

was set to be only 1 dB higher than the other region with its peak

power adjusted slightly above the overload threshold level

resulting in an occasional overload event. Each plot compares

the envelope response between a pulse that results in an overload

event to a pulse where the Σ-Δ ADC remains stable and includes a

zoom in region showing settling time to within 1% following

the large scale settling plot. Because the phase response recovers

two to three samples before the envelope response, the phase

response is not shown.

Note the following:

•

The AD6676 was configured for FIF = 300 MHz, BW =

100 MHz, and FADC = 3.2 GHz.

•

The absolute settling response for any decimation factor scales

with fDATA_IQ. For example, the settling time shown in Figure 77

is an additional seven samples at fDATA_IQ = 200 MSPS, thus

the absolute settling time is 35 ns (7 × 1/200 MSPS).

•

Selecting a decimation factor of 12 or 16 improves the absolute

settling time because it reduces the additive delay caused

by the last stage decimation filter.

1.0

0.95

0.96

0.97

0.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

101

103

105

107

109

111

113

115

SAMPLES

ZOOM-IN OF LARGE SCALE

SETTLING RESPONSE FOR 1% SETTLING

LARGE SCALE SETTLING

NO OVERLOAD/

RECOVERY

OVERLOAD/

RECOVERY

7 SAMPLES

@ 266.7MSPS

Figure 76. Comparison of Normalized IQ Magnitude Response for Decimate

by 12 Case When a Pulsed CW Waveform (10 ns Width) Is Just Below and

Above Peak Power Level, Resulting in ADC Overload

1.1

1.2

1.0

0.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05

1.06

1.07

1.08

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

SAMPLES

ZOOM-IN OF LARGE SCALE

SETTLING RESPONSE FOR 1% SETTLING

LARGE SCALE SETTLING

NO OVERLOAD/

RECOVERY

OVERLOAD/

RECOVERY

7 SAMPLES

@ 200MSPS

Figure 77. Comparison of Normalized IQ Magnitude Response for Decimate

by 16 Case When a Pulsed CW Waveform (10 ns Width) Is Just Below and

Above Peak Power Level, Resulting in ADC Overload

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